{"id":"https://openalex.org/W4409659342","doi":"https://doi.org/10.1109/jssc.2025.3558287","title":"A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS","display_name":"A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS","publication_year":2025,"publication_date":"2025-04-22","ids":{"openalex":"https://openalex.org/W4409659342","doi":"https://doi.org/10.1109/jssc.2025.3558287"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2025.3558287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3558287","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090865912","display_name":"Kai Li","orcid":"https://orcid.org/0000-0003-3251-931X"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Kai Li","raw_affiliation_strings":["School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038495391","display_name":"Mingqiang Huang","orcid":"https://orcid.org/0000-0002-7794-3985"},"institutions":[{"id":"https://openalex.org/I4210145761","display_name":"Shenzhen Institutes of Advanced Technology","ror":"https://ror.org/04gh4er46","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210145761"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingqiang Huang","raw_affiliation_strings":["Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China","institution_ids":["https://openalex.org/I4210145761"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036008947","display_name":"A. M. Li","orcid":null},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ang Li","raw_affiliation_strings":["School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091228336","display_name":"Shuxin Yang","orcid":"https://orcid.org/0000-0002-0794-7040"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuxin Yang","raw_affiliation_strings":["School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046207386","display_name":"Quan Cheng","orcid":"https://orcid.org/0000-0001-5519-3258"},"institutions":[{"id":"https://openalex.org/I22299242","display_name":"Kyoto University","ror":"https://ror.org/02kpeqv85","country_code":"JP","type":"education","lineage":["https://openalex.org/I22299242"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Quan Cheng","raw_affiliation_strings":["Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan","institution_ids":["https://openalex.org/I22299242"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034853402","display_name":"Hao Yu","orcid":"https://orcid.org/0000-0002-2674-4118"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Yu","raw_affiliation_strings":["School of Microelectronics, Southern University of Science and Technology, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Southern University of Science and Technology, Shenzhen, China","institution_ids":["https://openalex.org/I3045169105"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5090865912"],"corresponding_institution_ids":["https://openalex.org/I3045169105"],"apc_list":null,"apc_paid":null,"fwci":6.8108,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.96202003,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"60","issue":"10","first_page":"3790","last_page":"3801"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tops","display_name":"TOPS","score":0.7648293375968933},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6409007906913757},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.37695637345314026},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.34402579069137573},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.21329426765441895},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.11605009436607361}],"concepts":[{"id":"https://openalex.org/C2777675136","wikidata":"https://www.wikidata.org/wiki/Q835642","display_name":"TOPS","level":3,"score":0.7648293375968933},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6409007906913757},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.37695637345314026},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.34402579069137573},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.21329426765441895},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.11605009436607361},{"id":"https://openalex.org/C159737794","wikidata":"https://www.wikidata.org/wiki/Q124274","display_name":"Azimuth","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2025.3558287","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3558287","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7300000190734863}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W2289252105","https://openalex.org/W2553303224","https://openalex.org/W2588191434","https://openalex.org/W2593564159","https://openalex.org/W2625457103","https://openalex.org/W2895531329","https://openalex.org/W2904902077","https://openalex.org/W2945146780","https://openalex.org/W2950656546","https://openalex.org/W2963367920","https://openalex.org/W2982479999","https://openalex.org/W2997147213","https://openalex.org/W3015305895","https://openalex.org/W3020173600","https://openalex.org/W3025143601","https://openalex.org/W3114479342","https://openalex.org/W3130554079","https://openalex.org/W3163046230","https://openalex.org/W3185702163","https://openalex.org/W3205311052","https://openalex.org/W4206957512","https://openalex.org/W4240168186","https://openalex.org/W4280493494","https://openalex.org/W4285250061","https://openalex.org/W4317553465","https://openalex.org/W4319996342","https://openalex.org/W4360606495","https://openalex.org/W4379116018","https://openalex.org/W4387250389","https://openalex.org/W4387789586","https://openalex.org/W4396918219"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2811109569","https://openalex.org/W2385933648","https://openalex.org/W2381557761","https://openalex.org/W2935759653","https://openalex.org/W3105167352","https://openalex.org/W54078636","https://openalex.org/W2954470139"],"abstract_inverted_index":{"The":[0,85,138,180],"increasing":[1],"model":[2],"size":[3],"and":[4,41,65,77,132,151,174,192],"computational":[5],"load":[6],"of":[7,61,166],"deep":[8],"neural":[9,32],"networks":[10],"(DNNs)":[11],"present":[12],"a":[13,31,89,104,142],"significant":[14],"challenge":[15],"to":[16,37,51,56,93,129,156,168],"deploy":[17],"DNN":[18,53],"models":[19],"on":[20],"constrained":[21],"devices.":[22],"To":[23,68],"enhance":[24,157],"performance":[25],"without":[26],"compromising":[27],"accuracy,":[28],"we":[29],"introduce":[30],"architecture":[33],"search":[34],"(NAS)":[35],"method":[36],"develop":[38],"layer-wise":[39,62],"mixed-precision":[40,76,86,115,186],"mixed-sparsity":[42,78,139,196],"DNNs.":[43],"However,":[44],"the":[45,57,117,185,195],"optimization":[46],"cannot":[47],"be":[48],"directly":[49],"applied":[50],"existing":[52],"accelerators":[54,81],"due":[55],"specific":[58],"data":[59],"requirements":[60],"mixed":[63,66,120],"precision":[64,96],"sparsity.":[67],"address":[69],"this":[70,72],"issue,":[71],"research":[73],"proposes":[74],"separate":[75],"accelerators.":[79],"Both":[80],"demonstrate":[82],"cutting-edge":[83],"results.":[84],"accelerator":[87,140],"utilizes":[88],"split-and-combination":[90],"vector":[91,106],"(SCV)":[92],"re-use":[94],"variable":[95],"units":[97],"(1/2/4/8":[98],"bit)":[99],"at":[100,135,171],"each":[101],"layer":[102],"with":[103,149],"further":[105],"systolic":[107],"array":[108],"(VSA)":[109],"implementation.":[110],"By":[111],"optimizing":[112],"NAS":[113],"for":[114],"VGG-16,":[116],"VSA":[118,153],"achieves":[119,161],"energy":[121,164,190],"efficiency":[122,165,191],"reached":[123],"29.12":[124],"TOPS/W,":[125],"which":[126],"is":[127],"equivalent":[128,133],"2":[130],"bit":[131],"accuracy":[134,193],"4":[136],"bit.":[137],"introduces":[141],"log-scale":[143],"structured":[144],"sparse":[145],"encoding":[146],"strategy,":[147],"combined":[148],"MAC":[150],"group":[152],"(G-VSA)":[154],"optimization,":[155],"system":[158],"performance.":[159],"It":[160],"an":[162],"average":[163],"up":[167],"21.7":[169],"TOPS/W":[170],"0.7":[172],"V":[173],"400":[175],"MHz":[176],"using":[177],"28-nm":[178],"CMOS.":[179],"measured":[181],"results":[182],"show":[183],"that":[184],"chip":[187],"exhibits":[188],"better":[189],"than":[194],"chip.":[197]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}