{"id":"https://openalex.org/W4409763084","doi":"https://doi.org/10.1109/jssc.2025.3550254","title":"Corrections to \u201cDesign and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation\u201d","display_name":"Corrections to \u201cDesign and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation\u201d","publication_year":2025,"publication_date":"2025-04-24","ids":{"openalex":"https://openalex.org/W4409763084","doi":"https://doi.org/10.1109/jssc.2025.3550254"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2025.3550254","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3550254","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"erratum","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082332433","display_name":"Mohammadreza Zeinali","orcid":"https://orcid.org/0009-0002-8233-1198"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammadreza Zeinali","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0009-0002-8233-1198","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025807083","display_name":"Sudhakar Pamarti","orcid":"https://orcid.org/0000-0003-1457-7508"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar Pamarti","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-1457-7508","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"60","issue":"5","first_page":"1882","last_page":"1882"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.982200026512146,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.942300021648407,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.8640524744987488},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.7468552589416504},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6712525486946106},{"id":"https://openalex.org/keywords/spur","display_name":"Spur","score":0.6127290725708008},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.4853490889072418},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3579915463924408},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3503834009170532},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3419560194015503},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.312019407749176},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.26907292008399963},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.21789461374282837},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.20172211527824402},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16951501369476318},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.13198024034500122}],"concepts":[{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.8640524744987488},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.7468552589416504},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6712525486946106},{"id":"https://openalex.org/C2779821383","wikidata":"https://www.wikidata.org/wiki/Q7581537","display_name":"Spur","level":2,"score":0.6127290725708008},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.4853490889072418},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3579915463924408},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3503834009170532},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3419560194015503},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.312019407749176},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.26907292008399963},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.21789461374282837},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.20172211527824402},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16951501369476318},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.13198024034500122},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2025.3550254","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2025.3550254","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W4396982219"],"related_works":["https://openalex.org/W2390178440","https://openalex.org/W2776212486","https://openalex.org/W4404353518","https://openalex.org/W2350996794","https://openalex.org/W2964943829","https://openalex.org/W2516063142","https://openalex.org/W2080515223","https://openalex.org/W2367423162","https://openalex.org/W2371029054","https://openalex.org/W2169882863"],"abstract_inverted_index":{"This":[0],"article":[1,62],"provides":[2],"a":[3],"correction":[4,14],"to":[5,16],"an":[6],"error":[7],"in":[8],"our":[9],"previously":[10],"published":[11],"manuscript.":[12],"The":[13],"pertains":[15],"the":[17,22,34,49,53,56,60],"transfer":[18],"function":[19],"representation":[20],"of":[21,52,59],"main":[23,57],"fractional":[24],"frequency":[25],"synthesizer":[26],"structure":[27],"and":[28,55],"its":[29],"associated":[30],"components.":[31],"In":[32],"addition,":[33],"root":[35],"locus":[36],"analysis":[37],"requires":[38],"revision":[39],"based":[40],"on":[41],"this":[42],"correction.":[43],"These":[44],"modifications":[45],"do":[46],"not":[47],"affect":[48],"overall":[50],"validity":[51],"results,":[54],"conclusions":[58],"original":[61],"remain":[63],"unchanged.":[64]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}