{"id":"https://openalex.org/W4403598755","doi":"https://doi.org/10.1109/jssc.2024.3449115","title":"A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver","display_name":"A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver","publication_year":2024,"publication_date":"2024-10-21","ids":{"openalex":"https://openalex.org/W4403598755","doi":"https://doi.org/10.1109/jssc.2024.3449115"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2024.3449115","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2024.3449115","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114345221","display_name":"Chakravarti Bheemisetti","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Chakravarti Bheemisetti","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074008974","display_name":"K.N. Pandey","orcid":null},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Karunanidhan Pandey","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Bengaluru, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050145041","display_name":"Idan Lotan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Idan Lotan","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030578901","display_name":"Gadi Ori","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Gadi Ori","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005813911","display_name":"Ahmad Khairi","orcid":"https://orcid.org/0000-0001-7490-1037"},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Ahmad Khairi","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027703807","display_name":"Yoel Krupnik","orcid":"https://orcid.org/0000-0002-0724-8389"},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Yoel Krupnik","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040707597","display_name":"Udi Virobnik","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Udi Virobnik","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088433236","display_name":"Boyapati Subrahmanyam","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Boyapati Subrahmanyam","raw_affiliation_strings":["Synopsys, Dublin 15, Ireland","Synopsys, Dublin, D15E4FN Ireland"],"affiliations":[{"raw_affiliation_string":"Synopsys, Dublin 15, Ireland","institution_ids":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"raw_affiliation_string":"Synopsys, Dublin, D15E4FN Ireland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111376599","display_name":"Ariel Cohen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Ariel Cohen","raw_affiliation_strings":["Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel"],"affiliations":[{"raw_affiliation_string":"Mixed-Signal IP Group, Intel Corporation, Jerusalem, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080522900","display_name":"Nagendra Krishnapura","orcid":"https://orcid.org/0000-0002-8429-8910"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"facility","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nagendra Krishnapura","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology (IIT) Madras, Chennai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology (IIT) Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":4,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5114345221"],"corresponding_institution_ids":["https://openalex.org/I4210146682"],"apc_list":null,"apc_paid":null,"fwci":0.6263,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.69119662,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"60","issue":"4","first_page":"1486","last_page":"1499"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.8883908987045288},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7120133638381958},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.6459137797355652},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6266323328018188},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5263563394546509},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4838230013847351},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38364291191101074},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.33527305722236633},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.31635236740112305},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.26035088300704956},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1879534125328064},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1530105173587799},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.13409706950187683},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13186964392662048},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.05949684977531433}],"concepts":[{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.8883908987045288},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7120133638381958},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6459137797355652},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6266323328018188},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5263563394546509},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4838230013847351},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38364291191101074},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.33527305722236633},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.31635236740112305},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.26035088300704956},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1879534125328064},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1530105173587799},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.13409706950187683},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13186964392662048},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.05949684977531433}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2024.3449115","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2024.3449115","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7300000190734863}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1806144281","https://openalex.org/W1976807891","https://openalex.org/W1977030506","https://openalex.org/W2020287356","https://openalex.org/W2051102950","https://openalex.org/W2057781742","https://openalex.org/W2095089117","https://openalex.org/W2097216498","https://openalex.org/W2139664958","https://openalex.org/W2155589054","https://openalex.org/W2296644030","https://openalex.org/W2343222450","https://openalex.org/W2537775509","https://openalex.org/W2772829777","https://openalex.org/W2801373858","https://openalex.org/W2907232526","https://openalex.org/W2929858042","https://openalex.org/W3000059814","https://openalex.org/W3019221822","https://openalex.org/W3042078347","https://openalex.org/W3132180131","https://openalex.org/W3167271488","https://openalex.org/W4220765634","https://openalex.org/W4293143561","https://openalex.org/W4313058498","https://openalex.org/W4313467221","https://openalex.org/W4323896642"],"related_works":["https://openalex.org/W3029046703","https://openalex.org/W2145876553","https://openalex.org/W2139221936","https://openalex.org/W2017861587","https://openalex.org/W2600032170","https://openalex.org/W2790811635","https://openalex.org/W2019727651","https://openalex.org/W1999544091","https://openalex.org/W2065974882","https://openalex.org/W1911569504"],"abstract_inverted_index":{"This":[0,92,114],"article":[1],"presents":[2],"a":[3,58,62,72,95,106,120],"1.75-GS/s":[4],"single-channel":[5],"7-bit":[6,63],"successive":[7],"approximation":[8],"register":[9],"(SAR)":[10],"analog-to-digital":[11],"converter":[12],"(ADC)":[13],"that":[14],"is":[15,29,45,57,69,117],"based":[16],"on":[17],"loop-unrolled":[18],"architecture":[19],"with":[20],"N-comparators":[21],"for":[22,61,129],"N-bits.":[23],"A":[24,39],"memory-less":[25],"fully":[26],"asynchronous":[27],"SAR":[28,64,115],"proposed":[30,46],"to":[31,47,94,125],"lower":[32],"power":[33],"consumption":[34],"and":[35,52,88,105],"reduce":[36],"design":[37],"complexity.":[38],"double-tail":[40],"feed-backward":[41],"(DTFB)":[42],"dynamic":[43],"comparator":[44],"meet":[48],"the":[49],"required":[50],"speed":[51],"minimize":[53],"thermal":[54],"noise,":[55],"which":[56],"critical":[59],"parameter":[60],"ADC.":[65],"The":[66,76],"prototype":[67],"ADC":[68,77,116,124],"implemented":[70],"in":[71,119,131],"3-nm":[73],"CMOS":[74],"process.":[75],"achieves":[78],"an":[79,132],"SNDR/SFDR":[80],"of":[81,99,102,109],"37/49":[82],"dB":[83,111],"at":[84,112],"Nyquist,":[85],"0.00055-mm2":[86],"area,":[87],"consumes":[89],"0.69-mW":[90],"power.":[91],"leads":[93],"best-in-class":[96],"Walden":[97],"figure":[98],"merit":[100],"(FoMw)":[101],"6.9":[103],"fJ/conv.-step":[104],"Schreier":[107],"FoM":[108],"158":[110],"Nyquist.":[113],"used":[118],"64-way":[121],"time-interleaved":[122],"(TI)":[123],"achieve":[126],"112-GS/s":[127],"operation":[128],"use":[130],"ADC-based":[133],"224-Gb/s":[134],"PAM4":[135],"SerDes":[136],"receiver.":[137]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2024-10-22T00:00:00"}