{"id":"https://openalex.org/W4388469893","doi":"https://doi.org/10.1109/jssc.2023.3326094","title":"eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters","display_name":"eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters","publication_year":2023,"publication_date":"2023-11-07","ids":{"openalex":"https://openalex.org/W4388469893","doi":"https://doi.org/10.1109/jssc.2023.3326094"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2023.3326094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2023.3326094","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031054921","display_name":"Shanshan Xie","orcid":"https://orcid.org/0000-0001-8411-3050"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shanshan Xie","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA","Google LLC, Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-8411-3050","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078795733","display_name":"Can Ni","orcid":"https://orcid.org/0009-0008-5118-8601"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Can Ni","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Google LLC, Sunnyvale, CA, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0008-5118-8601","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015176330","display_name":"Aseem Sayal","orcid":"https://orcid.org/0000-0003-3078-9498"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aseem Sayal","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA","Google LLC, Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-3078-9498","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023812483","display_name":"Pulkit Jain","orcid":"https://orcid.org/0000-0001-5708-9761"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pulkit Jain","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Google LLC, Sunnyvale, CA, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA","Google LLC, Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-3500-5007","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003048953","display_name":"Jaydeep P. Kulkarni","orcid":"https://orcid.org/0000-0002-0258-6776"},"institutions":[{"id":"https://openalex.org/I1291425158","display_name":"Google (United States)","ror":"https://ror.org/00njsd438","country_code":"US","type":"company","lineage":["https://openalex.org/I1291425158","https://openalex.org/I4210128969"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaydeep P. Kulkarni","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","Intel Circuit Research Laboratory, Hillsboro, OR, USA","Google LLC, Sunnyvale, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-0258-6776","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Intel Circuit Research Laboratory, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Google LLC, Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I1291425158"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.9452,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.91674183,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":"59","issue":"6","first_page":"1950","last_page":"1961"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5561938285827637},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4494752287864685},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3451992869377136},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3347572088241577},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32122603058815},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21003198623657227}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5561938285827637},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4494752287864685},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3451992869377136},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3347572088241577},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32122603058815},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21003198623657227}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2023.3326094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2023.3326094","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6499999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1966939297","https://openalex.org/W1995562189","https://openalex.org/W1998808035","https://openalex.org/W2014651988","https://openalex.org/W2035713928","https://openalex.org/W2144354855","https://openalex.org/W2160815625","https://openalex.org/W2194775991","https://openalex.org/W2212165050","https://openalex.org/W2271840356","https://openalex.org/W2591601611","https://openalex.org/W2604319603","https://openalex.org/W2776589185","https://openalex.org/W2792893539","https://openalex.org/W2895842071","https://openalex.org/W2909308379","https://openalex.org/W2920326572","https://openalex.org/W2921351161","https://openalex.org/W2922487710","https://openalex.org/W2922523256","https://openalex.org/W2938922982","https://openalex.org/W2979874885","https://openalex.org/W2985229340","https://openalex.org/W3000301330","https://openalex.org/W3015590138","https://openalex.org/W3015980402","https://openalex.org/W3016014942","https://openalex.org/W3016021860","https://openalex.org/W3016147292","https://openalex.org/W3026786299","https://openalex.org/W3048746542","https://openalex.org/W3097655915","https://openalex.org/W3099871312","https://openalex.org/W3135701542","https://openalex.org/W4286571868","https://openalex.org/W4360605725","https://openalex.org/W6694517276"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,8,168],"compute-in-memory":[4],"(CIM)":[5],"architecture":[6],"for":[7,33,77,265],"large-scale":[9,268],"machine":[10],"learning":[11],"(ML)":[12],"accelerator,":[13,82],"which":[14,83,129,243],"employs":[15],"<inline-formula":[16,44],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[17,45,228],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[18,46],"<tex-math":[19,47],"notation=\"LaTeX\">$1T1C$</tex-math>":[20,48],"</inline-formula>":[21,49],"embedded":[22],"dynamic":[23,160],"random":[24],"access":[25],"memory":[26,69],"(eDRAM)":[27],"bitcells":[28],"as":[29],"charge":[30],"domain":[31,115,155],"circuits":[32],"convolution":[34,147],"neural":[35],"network":[36],"(CNN)":[37],"multiply-accumulation-averaging":[38],"(MAV)":[39],"computations.":[40],"By":[41],"repurposing":[42],"existing":[43],"eDRAM":[50,118,134,249],"columns":[51],"to":[52,113,152,174,236],"construct":[53],"an":[54,78,157,247],"adaptive":[55,159],"data":[56,137,142],"converter,":[57],"dot-product,":[58],"averaging,":[59],"pooling,":[60],"and":[61,90,139,178,195,209,224,258],"rectified":[62],"linear":[63],"unit":[64],"(ReLU)":[65],"activation":[66],"on":[67,117],"the":[68,71,75,86,92,95,100,126,133,146,153,187,193,196,199,202,239],"array,":[70,135],"eDRAM-CIM":[72,101,183,241],"design":[73],"eliminates":[74],"need":[76],"extra":[79],"dedicated":[80],"hardware":[81,87],"significantly":[84],"reduces":[85],"implementation":[88],"cost":[89],"increases":[91],"reconfigurability":[93],"of":[94,171,198],"CIM":[96,270],"computation":[97],"circuit.":[98],"In":[99,144],"design,":[102],"8":[103,206,210],"b":[104,207,211],"digital":[105,154],"inputs":[106],"from":[107],"image":[108],"pixel":[109],"values":[110],"are":[111,130,149],"converted":[112],"analog":[114],"directly":[116],"columns.":[119],"The":[120],"dot-product":[121,172],"is":[122,234],"computed":[123],"without":[124],"disturbing":[125],"kernel":[127],"weights,":[128],"stored":[131],"in":[132,186,246,267],"preventing":[136],"duplication":[138],"additional":[140],"intra-memory":[141],"movement.":[143],"addition,":[145],"results":[148],"transferred":[150],"back":[151],"using":[156,201],"in-eDRAM":[158],"range":[161,170],"successive-approximation":[162],"(SAR)":[163],"analog-to-digital":[164],"converter":[165],"(ADC)":[166],"utilizing":[167],"narrow":[169],"distribution":[173],"reduce":[175],"ADC":[176],"latency":[177],"energy.":[179],"A":[180,231],"16":[181],"Kb":[182],"prototype,":[184],"implemented":[185],"65":[188],"nm":[189],"CMOS":[190],"process,":[191],"demonstrates":[192],"concept":[194],"functionality":[197],"test-chip":[200],"CIFAR-10":[203],"dataset":[204],"with":[205],"input":[208],"signed":[212],"weight,":[213],"achieving":[214],"90.77%":[215],"accuracy,":[216],"4.71":[217],"GOPS":[218],"throughput,":[219],"4.76":[220],"TOPS/W":[221],"energy":[222,254],"efficiency,":[223],"8.26":[225],"GOPS/mm":[226],"<sup":[227],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[229],".":[230],"scalability":[232],"analysis":[233],"developed":[235],"show":[237],"that":[238],"presented":[240],"approach,":[242],"was":[244],"adopted":[245],"advanced":[248],"technology":[250],"node,":[251],"shows":[252],"promising":[253],"efficiency":[255],"(11.21":[256],"TOPS/W)":[257],"throughput":[259],"(22.2":[260],"TOPS),":[261],"suggesting":[262],"its":[263],"potential":[264],"application":[266],"energy-efficient":[269],"designs.":[271]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":12},{"year":2024,"cited_by_count":6}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
