{"id":"https://openalex.org/W4285290407","doi":"https://doi.org/10.1109/jssc.2022.3171790","title":"Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier","display_name":"Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier","publication_year":2022,"publication_date":"2022-05-18","ids":{"openalex":"https://openalex.org/W4285290407","doi":"https://doi.org/10.1109/jssc.2022.3171790"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2022.3171790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2022.3171790","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076916386","display_name":"R. S. Ashwin Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]},{"id":"https://openalex.org/I94234084","display_name":"Indian Institute of Technology Kanpur","ror":"https://ror.org/05pjsgx75","country_code":"IN","type":"education","lineage":["https://openalex.org/I94234084"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. S. Ashwin Kumar","raw_affiliation_strings":["Electrical Engineering Department, IIT Madras, Chennai, India","Electrical Engineering Department, IIT Kanpur, Kanpur, India"],"raw_orcid":"https://orcid.org/0000-0001-8876-1469","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, IIT Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]},{"raw_affiliation_string":"Electrical Engineering Department, IIT Kanpur, Kanpur, India","institution_ids":["https://openalex.org/I94234084"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080522900","display_name":"Nagendra Krishnapura","orcid":"https://orcid.org/0000-0002-8429-8910"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nagendra Krishnapura","raw_affiliation_strings":["Electrical Engineering Department, IIT Madras, Chennai, India"],"raw_orcid":"https://orcid.org/0000-0002-8429-8910","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, IIT Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075518405","display_name":"Paramita Banerjee","orcid":"https://orcid.org/0000-0001-7716-9996"},"institutions":[{"id":"https://openalex.org/I24676775","display_name":"Indian Institute of Technology Madras","ror":"https://ror.org/03v0r5n49","country_code":"IN","type":"education","lineage":["https://openalex.org/I24676775"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Paramita Banerjee","raw_affiliation_strings":["Electrical Engineering Department, IIT Madras, Chennai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, IIT Madras, Chennai, India","institution_ids":["https://openalex.org/I24676775"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.2951,"has_fulltext":false,"cited_by_count":99,"citation_normalized_percentile":{"value":0.98048112,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"57","issue":"11","first_page":"3384","last_page":"3395"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/operational-transconductance-amplifier","display_name":"Operational transconductance amplifier","score":0.6267579793930054},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5855870246887207},{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.5715442895889282},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.5289416909217834},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.4785792827606201},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41470903158187866},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3833962082862854},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.36904633045196533},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3675839304924011},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3439379930496216},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.32861170172691345},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.2131926715373993},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20230573415756226},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.13180652260780334},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10753840208053589}],"concepts":[{"id":"https://openalex.org/C58117264","wikidata":"https://www.wikidata.org/wiki/Q1239595","display_name":"Operational transconductance amplifier","level":5,"score":0.6267579793930054},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5855870246887207},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.5715442895889282},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.5289416909217834},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.4785792827606201},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41470903158187866},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3833962082862854},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.36904633045196533},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3675839304924011},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3439379930496216},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.32861170172691345},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.2131926715373993},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20230573415756226},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.13180652260780334},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10753840208053589}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2022.3171790","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2022.3171790","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W605564925","https://openalex.org/W1533614470","https://openalex.org/W1594843507","https://openalex.org/W1621379163","https://openalex.org/W1936328962","https://openalex.org/W2019274525","https://openalex.org/W2026225680","https://openalex.org/W2042029813","https://openalex.org/W2123616685","https://openalex.org/W2133313666","https://openalex.org/W2159734412","https://openalex.org/W2166307883","https://openalex.org/W2166948256","https://openalex.org/W2522828564","https://openalex.org/W2537592904","https://openalex.org/W2587606799","https://openalex.org/W2602440913","https://openalex.org/W2777864162","https://openalex.org/W2788013190","https://openalex.org/W2896117359","https://openalex.org/W2908282098","https://openalex.org/W2963592132","https://openalex.org/W2979467914","https://openalex.org/W3010868036","https://openalex.org/W3015354097","https://openalex.org/W3112125306","https://openalex.org/W4205751875"],"related_works":["https://openalex.org/W2783539788","https://openalex.org/W4293528144","https://openalex.org/W2792031931","https://openalex.org/W2341419291","https://openalex.org/W3113698884","https://openalex.org/W2074850648","https://openalex.org/W3134607556","https://openalex.org/W2953413763","https://openalex.org/W2134780641","https://openalex.org/W4235119538"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,8,53,56,75,81,159,180,191,200,214,218],"delta\u2013sigma":[4],"modulator":[5,205],"(DSM)":[6],"using":[7],"cascoded":[9,15,50,174,189],"floating-inverter-based":[10],"dynamic":[11,16,77],"amplifier.":[12,186],"The":[13,204],"proposed":[14],"amplifier":[17,47],"achieves":[18],"more":[19,177],"than":[20,30,179],"50-dB":[21],"dc":[22],"gain":[23],"while":[24,210],"maintaining":[25],"an":[26,63],"HD3":[27],"of":[28,118,158,220],"better":[29],"\u2013110":[31],"dBc":[32],"for":[33,66,116],"signal":[34],"swings":[35],"less":[36,150],"than$300~\\mathrm":[37],"{mV_{ppd}}$.":[38],"Compared":[39],"to":[40,126,152],"the":[41,49,90,95,99,108,119,123,128,136,144,156,173,188,223],"previously":[42],"reported":[43],"two-stage":[44],"floating":[45,109],"inverter":[46,110],"(FIA),":[48],"FIA":[51,175],"has":[52,80,194],"lower":[54],"and":[55,140,170,197],"process":[57],"invariant":[58],"input-referred":[59],"noise,":[60],"making":[61],"it":[62,148],"ideal":[64],"choice":[65],"high-resolution":[67],"ADCs.":[68],"We":[69,166],"also":[70,167],"show":[71,171],"that,":[72,106],"when":[73,107],"such":[74],"single-stage":[76],"amplifier,":[78],"which":[79],"time-varying":[82],"transconductance,":[83],"is":[84,122,149,176,226],"used":[85],"in":[86,113,163,199],"closed-loop":[87],"switched-capacitor":[88],"circuits,":[89],"settling":[91,100],"bandwidth":[92,219],"depends":[93,133],"on":[94,135,143],"average":[96,131],"transconductance$G_{m,\\rm":[97],"avg}$during":[98],"interval.":[101],"A":[102],"detailed":[103],"analysis":[104],"reveals":[105],"structure":[111],"operates":[112],"weak":[114,164],"inversion":[115],"most":[117],"time":[120],"(which":[121],"power-efficient":[124,178],"way":[125],"bias":[127],"amplifier),":[129],"this":[130],"transconductance":[132,157,185],"strongly":[134],"reservoir":[137],"capacitance":[138],"value":[139],"only":[141],"weakly":[142],"transistor":[145],"dimensions.":[146],"Besides,":[147],"sensitive":[151],"temperature":[153],"variations,":[154],"unlike":[155],"conventional":[160,181],"OTA":[161],"biased":[162,183],"inversion.":[165],"quantitatively":[168],"derive":[169],"that":[172],"static-current":[182],"operational":[184],"Using":[187],"FIA,":[190],"discrete-time":[192],"DSM":[193],"been":[195],"designed":[196],"fabricated":[198],"180-nm":[201],"CMOS":[202],"process.":[203],"runs":[206],"at":[207],"3.072":[208],"MHz":[209],"consuming":[211],"189$\\mu":[212],"\\text{A}$from":[213],"1.8-V":[215],"supply.":[216],"In":[217],"24":[221],"kHz,":[222],"measured":[224],"SNR/SNDR/SFDR":[225],"96.4/96.2/114":[227],"dB,":[228],"respectively.":[229]},"counts_by_year":[{"year":2026,"cited_by_count":10},{"year":2025,"cited_by_count":31},{"year":2024,"cited_by_count":30},{"year":2023,"cited_by_count":22},{"year":2022,"cited_by_count":5},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}
