{"id":"https://openalex.org/W3213347303","doi":"https://doi.org/10.1109/jssc.2021.3122986","title":"A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications","display_name":"A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications","publication_year":2021,"publication_date":"2021-11-05","ids":{"openalex":"https://openalex.org/W3213347303","doi":"https://doi.org/10.1109/jssc.2021.3122986","mag":"3213347303"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2021.3122986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3122986","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091072278","display_name":"Dongseok Shin","orcid":"https://orcid.org/0000-0003-0014-2626"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Dongseok Shin","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-0014-2626","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100661079","display_name":"Hyung Seok Kim","orcid":"https://orcid.org/0000-0003-2386-7945"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyung Seok Kim","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-2386-7945","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036989858","display_name":"Chuanchang Liu","orcid":"https://orcid.org/0000-0002-0418-9889"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chuan-Chang Liu","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011274694","display_name":"Priya Wali","orcid":"https://orcid.org/0000-0002-1996-9319"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Priya Wali","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0002-1996-9319","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018682047","display_name":"Savyasaachi Keshava Murthy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Savyasaachi Keshava Murthy","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018623391","display_name":"Y. Fan","orcid":"https://orcid.org/0000-0001-5914-2765"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yongping Fan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0001-5914-2765","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5091072278"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.8134,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.72698336,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"57","issue":"6","first_page":"1736","last_page":"1748"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8288705348968506},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.7172424793243408},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.6262223720550537},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.5838634371757507},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.5446746349334717},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5399418473243713},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5235832929611206},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.46918487548828125},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.46791890263557434},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.44719764590263367},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.41552940011024475},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.4150136709213257},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4108765721321106},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3879597783088684},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3386552929878235},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29868611693382263},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23614755272865295},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.20595142245292664},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13098770380020142}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8288705348968506},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.7172424793243408},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.6262223720550537},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.5838634371757507},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.5446746349334717},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5399418473243713},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5235832929611206},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.46918487548828125},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.46791890263557434},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.44719764590263367},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.41552940011024475},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.4150136709213257},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4108765721321106},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3879597783088684},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3386552929878235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29868611693382263},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23614755272865295},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.20595142245292664},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13098770380020142},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2021.3122986","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3122986","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8199999928474426,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W2013632533","https://openalex.org/W2055978681","https://openalex.org/W2062952706","https://openalex.org/W2098907338","https://openalex.org/W2117974234","https://openalex.org/W2144253779","https://openalex.org/W2153374144","https://openalex.org/W2177833654","https://openalex.org/W2321859177","https://openalex.org/W2471244034","https://openalex.org/W2792808087","https://openalex.org/W2802479922","https://openalex.org/W2891924334","https://openalex.org/W2908054846","https://openalex.org/W2920848205","https://openalex.org/W2920852491","https://openalex.org/W2921046765","https://openalex.org/W3015425606","https://openalex.org/W3015563675","https://openalex.org/W3015749170","https://openalex.org/W3015797764","https://openalex.org/W3133618096","https://openalex.org/W3135235705","https://openalex.org/W3135411826","https://openalex.org/W3135783513","https://openalex.org/W6749183639"],"related_works":["https://openalex.org/W3095898867","https://openalex.org/W2099990255","https://openalex.org/W1975478216","https://openalex.org/W1994421603","https://openalex.org/W3207257560","https://openalex.org/W2167684701","https://openalex.org/W2110035284","https://openalex.org/W2151357254","https://openalex.org/W1915959989","https://openalex.org/W2358217230"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,15,50,54,59,121,173,183,200,227,241],"23.9\u201329.4":[4],"GHz":[5,45,70,79,88,132],"digital":[6],"<italic":[7,203,233],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[8,204,234,254],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">LC</i>":[9,205,235],"-phase-locked":[10],"loop":[11,126],"(PLL)":[12],"architecture":[13],"with":[14,37,199,225],"low":[16],"phase":[17],"noise":[18],"(PN)":[19],"and":[20,43,68,104,118,123,169,246],"power-efficient":[21,124],"coupled":[22,48,61,217],"frequency":[23,33,56,218],"doubler":[24,34,57,219],"for":[25],"224":[26,194],"Gb/s":[27,195],"PAM-4":[28,196],"transmitter":[29,180],"clocking.":[30],"The":[31,130,159,232],"proposed":[32,160,216],"is":[35,102,108,128,135,162],"designed":[36],"two":[38,95],"oscillators":[39,71,96],"running":[40],"at":[41,178],"14":[42,67,78,131],"28":[44,69,87],"which":[46,147,189],"are":[47],"by":[49,92],"transformer.":[51],"Compared":[52,198],"to":[53,137],"conventional":[55],"or":[58],"two-way":[60],"oscillator,":[62],"the":[63,66,77,86,94,98,100,112,138,144,152,156,170,179,191,212,215],"coupling":[64],"between":[65],"provides":[72],"extra":[73],"PN":[74,84,113,224],"reduction":[75],"as":[76],"oscillator":[80,133,208],"can":[81],"achieve":[82],"lower":[83,223],"than":[85,143],"one.":[89],"In":[90],"addition,":[91],"stacking":[93],"through":[97],"transformer,":[99],"current":[101],"reused":[103],"hence":[105],"power":[106,149,229],"consumption":[107,230],"reduced.":[109],"To":[110],"optimize":[111],"performance":[114],"across":[115],"process,":[116],"voltage,":[117],"temperature":[119],"(PVT),":[120],"compact":[122],"frequency-tracking":[125],"(FTL)":[127],"implemented.":[129],"output":[134,181],"fed":[136],"PLL":[139,161,171],"feedback":[140,157],"divider":[141,154],"rather":[142],"doubled":[145],"output,":[146],"enables":[148,190],"saving":[150],"in":[151,155,164],"prescaler":[153],"path.":[158],"fabricated":[163],"10":[165],"nm":[166],"FinFET":[167],"technology":[168],"achieves":[172,220],"65":[174],"fs":[175],"random":[176],"jitter":[177],"after":[182],"1st-order":[184],"4":[185],"MHz-BW":[186],"CDR":[187],"filtering":[188],"industry\u2019s":[192],"first":[193],"transmitter.":[197],"reference":[201],"NMOS-GM":[202],"-digitally":[206],"controlled":[207],"(DCO)":[209],"implemented":[210],"on":[211],"same":[213],"die,":[214],"4.75":[221],"dB":[222],"only":[226],"25%":[228],"increase.":[231],"-PLL":[236],"consumes":[237],"17.1":[238],"mW":[239],"from":[240],"0.8/1.0":[242],"V":[243],"regulated":[244],"supply":[245],"occupies":[247],"an":[248],"area":[249],"of":[250],"0.088":[251],"mm":[252],"<sup":[253],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[255],".":[256]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
