{"id":"https://openalex.org/W3194602580","doi":"https://doi.org/10.1109/jssc.2021.3104540","title":"A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver","display_name":"A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver","publication_year":2021,"publication_date":"2021-08-23","ids":{"openalex":"https://openalex.org/W3194602580","doi":"https://doi.org/10.1109/jssc.2021.3104540","mag":"3194602580"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2021.3104540","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3104540","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039817567","display_name":"Anjana Dissanayake","orcid":"https://orcid.org/0000-0003-3466-5994"},"institutions":[{"id":"https://openalex.org/I135218257","display_name":"Swiss Center for Electronics and Microtechnology (Switzerland)","ror":"https://ror.org/05nrrsx06","country_code":"CH","type":"company","lineage":["https://openalex.org/I135218257"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Anjana Dissanayake","raw_affiliation_strings":["CSEM SA, Neuch\u00e2tel, Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-3466-5994","affiliations":[{"raw_affiliation_string":"CSEM SA, Neuch\u00e2tel, Switzerland","institution_ids":["https://openalex.org/I135218257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062662033","display_name":"Henry L. Bishop","orcid":"https://orcid.org/0000-0001-7155-6434"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Henry L. Bishop","raw_affiliation_strings":["Amazon.com, Inc., Redmond, WA, USA"],"raw_orcid":"https://orcid.org/0000-0001-7155-6434","affiliations":[{"raw_affiliation_string":"Amazon.com, Inc., Redmond, WA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073617259","display_name":"Steven M. Bowers","orcid":"https://orcid.org/0000-0002-4243-8663"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven M. Bowers","raw_affiliation_strings":["Department of Electrical and Computer engineering, University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-4243-8663","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benton H. Calhoun","raw_affiliation_strings":["Department of Electrical and Computer engineering, University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-3770-5050","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3603,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.88951907,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":"57","issue":"3","first_page":"917","last_page":"931"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12791","display_name":"Full-Duplex Wireless Communications","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/notation","display_name":"Notation","score":0.5258857607841492},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.49115893244743347},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4631684720516205},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4138946831226349},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.40520739555358887},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.33004552125930786},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.32864218950271606},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3284415006637573},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1662541925907135},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.16431480646133423},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.14732694625854492},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.13726213574409485},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09883865714073181}],"concepts":[{"id":"https://openalex.org/C45357846","wikidata":"https://www.wikidata.org/wiki/Q2001982","display_name":"Notation","level":2,"score":0.5258857607841492},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.49115893244743347},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4631684720516205},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4138946831226349},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40520739555358887},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.33004552125930786},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.32864218950271606},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3284415006637573},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1662541925907135},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.16431480646133423},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.14732694625854492},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.13726213574409485},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09883865714073181}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2021.3104540","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3104540","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6642971735","display_name":null,"funder_award_id":"EEC-1160483","funder_id":"https://openalex.org/F4320337394","funder_display_name":"Division of Engineering Education and Centers"}],"funders":[{"id":"https://openalex.org/F4320337394","display_name":"Division of Engineering Education and Centers","ror":"https://ror.org/050rnw378"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2035100086","https://openalex.org/W2110144707","https://openalex.org/W2128207004","https://openalex.org/W2139890817","https://openalex.org/W2289760835","https://openalex.org/W2460786723","https://openalex.org/W2566236549","https://openalex.org/W2734928650","https://openalex.org/W2798342858","https://openalex.org/W2802901319","https://openalex.org/W2939973106","https://openalex.org/W2965649329","https://openalex.org/W2979948651","https://openalex.org/W2997584738","https://openalex.org/W3015157160","https://openalex.org/W3015269242","https://openalex.org/W3020324382","https://openalex.org/W3048477082","https://openalex.org/W3125102979","https://openalex.org/W3135424026"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2504004674","https://openalex.org/W1987679298","https://openalex.org/W2963177394","https://openalex.org/W4313359513","https://openalex.org/W2498744856","https://openalex.org/W4390482104","https://openalex.org/W322408318","https://openalex.org/W149041114","https://openalex.org/W1965815883"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,15,39,117,131,142],"highly":[4],"integrated":[5,189],"2.4-GHz":[6],"wake-up":[7],"receiver":[8],"(WuRX)":[9],"achieving":[10],"91.5":[11],"dBm":[12],"sensitivity":[13],"with":[14,57,116,188],"state-of-the-art":[16],"power":[17],"and":[18,84,151,172,184],"latency":[19,74,95],"combination":[20],"of":[21,108,158],"2":[22,109],"<inline-formula":[23,64,76,85,97,173],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[24,65,77,86,98,174],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[25,66,78,87,99,175],"<tex-math":[26,67,79,88,100,176],"notation=\"LaTeX\">$\\mu":[27,80,101],"\\text{W}$":[28,81,102],"</tex-math></inline-formula>":[29,70,82,91,103,178],"at":[30,71,92,105,161],"100":[31],"ms.":[32],"The":[33,113,134],"proposed":[34],"within-packet":[35],"duty-cycling":[36],"method":[37],"employs":[38],"carrier-sense":[40],"mechanism":[41],"to":[42,140,145,193],"turn":[43],"off":[44],"the":[45,54,106,127,195],"WuRX":[46],"early":[47],"under":[48],"idle":[49],"channel":[50,149],"conditions,":[51],"which":[52],"reduces":[53],"dc-power":[55,128],"compared":[56],"conventional":[58],"asynchronous":[59],"packet-level":[60],"duty":[61],"cycling":[62],"by":[63],"notation=\"LaTeX\">$9\\times":[68],"$":[69,90],"10":[72],"ms":[73],"(21":[75],")":[83,104],"notation=\"LaTeX\">$2\\times":[89],"1":[93],"s":[94],"(0.9":[96],"cost":[107],"dB":[110,160],"in":[111,166,197],"sensitivity.":[112],"uncertain-IF":[114],"topology":[115],"phase-locked":[118],"loop":[119],"(PLL)-aided":[120],"event-driven":[121],"calibrated":[122],"local-oscillator":[123],"(LO)":[124],"helps":[125],"reduce":[126],"while":[129],"maintaining":[130],"fast":[132],"startup.":[133],"channel-embedded":[135],"OOK":[136],"scheme":[137],"is":[138,186],"used":[139],"create":[141],"deterministic":[143],"IF":[144],"enable":[146],"baseband":[147],"(BB)":[148],"selection":[150],"achieve":[152],"continuous":[153],"wave":[154],"(CW)":[155],"interference":[156],"tolerance":[157],"\u221247":[159],"20":[162],"MHz":[163],"offset.":[164],"Fabricated":[165],"65":[167],"nm":[168],"CMOS,":[169],"input":[170],"matching":[171],"notation=\"LaTeX\">$LC$":[177],"oscillator":[179],"are":[180],"all":[181],"implemented":[182],"on-chip,":[183],"operation":[185],"demonstrated":[187],"low":[190],"dropout":[191],"regulators":[192],"capture":[194],"degradations":[196],"realistic":[198],"system":[199],"integration.":[200]},"counts_by_year":[{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":7}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
