{"id":"https://openalex.org/W3189958273","doi":"https://doi.org/10.1109/jssc.2021.3101046","title":"A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL","display_name":"A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL","publication_year":2021,"publication_date":"2021-11-01","ids":{"openalex":"https://openalex.org/W3189958273","doi":"https://doi.org/10.1109/jssc.2021.3101046","mag":"3189958273"},"language":"en","primary_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3101046","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/9583614/09511426.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-state Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/4/9583614/09511426.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049355767","display_name":"Jianglin Du","orcid":"https://orcid.org/0000-0002-4533-3576"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933","https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Jianglin Du","raw_affiliation_string":"School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland.","raw_affiliation_strings":["School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland."]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050565374","display_name":"Teerachot Siriburanon","orcid":"https://orcid.org/0000-0003-1658-9596"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933","https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Teerachot Siriburanon","raw_affiliation_string":"School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland.","raw_affiliation_strings":["School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland."]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008837666","display_name":"Yizhe Hu","orcid":"https://orcid.org/0000-0003-3685-7666"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933","https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Yizhe Hu","raw_affiliation_string":"School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland.","raw_affiliation_strings":["School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland."]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035022236","display_name":"Vivek Govindaraj","orcid":null},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933","https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Vivek Govindaraj","raw_affiliation_string":"School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland.","raw_affiliation_strings":["School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland."]},{"author_position":"last","author":{"id":"https://openalex.org/A5027017637","display_name":"Robert Bogdan Staszewski","orcid":"https://orcid.org/0000-0001-9848-1129"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933","https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Robert Bogdan Staszewski","raw_affiliation_string":"School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland.","raw_affiliation_strings":["School of Electrical & Electronic Engineering, University College Dublin, Dublin, Ireland."]}],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"has_fulltext":false,"cited_by_count":10,"cited_by_percentile_year":{"min":91,"max":92},"biblio":{"volume":"56","issue":"11","first_page":"3445","last_page":"3457"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Phase-Locked Loops in High-Speed Circuits","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Phase-Locked Loops in High-Speed Circuits","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog Circuit Design for Biomedical Applications","score":0.9976,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9945,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"keyword":"reference-waveform","score":0.25}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7261854},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.6802286},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.56362426},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5513699},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5040099},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.41413647},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.405192},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3654483},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.35673136},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2546449},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23873872},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18041357},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11827615},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3101046","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/9583614/09511426.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-state Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","version":"publishedVersion","is_accepted":true,"is_published":true}],"best_oa_location":{"is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2021.3101046","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/9583614/09511426.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-state Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","version":"publishedVersion","is_accepted":true,"is_published":true},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.76,"display_name":"Affordable and clean energy"}],"grants":[{"funder":"https://openalex.org/F4320320847","funder_display_name":"Science Foundation Ireland","award_id":"14/RP/I2921"}],"referenced_works_count":24,"referenced_works":["https://openalex.org/W1544882865","https://openalex.org/W1994184480","https://openalex.org/W2054933520","https://openalex.org/W2097406868","https://openalex.org/W2103868891","https://openalex.org/W2120500930","https://openalex.org/W2131053965","https://openalex.org/W2139625690","https://openalex.org/W2142610168","https://openalex.org/W2163630970","https://openalex.org/W2316615363","https://openalex.org/W2346049708","https://openalex.org/W2611384543","https://openalex.org/W2801373858","https://openalex.org/W2810207282","https://openalex.org/W2896904406","https://openalex.org/W2901134537","https://openalex.org/W2901368319","https://openalex.org/W2913416661","https://openalex.org/W2921886179","https://openalex.org/W2964943829","https://openalex.org/W2988067473","https://openalex.org/W3040994238","https://openalex.org/W3093748429"],"related_works":["https://openalex.org/W2766503024","https://openalex.org/W4206637278","https://openalex.org/W2781247653","https://openalex.org/W4386005305","https://openalex.org/W3082051559","https://openalex.org/W1682621979","https://openalex.org/W3173198409","https://openalex.org/W4386214543","https://openalex.org/W1969988626","https://openalex.org/W1571672972"],"ngrams_url":"https://api.openalex.org/works/W3189958273/ngrams","abstract_inverted_index":{"This":[0,143],"article":[1],"presents":[2],"a":[3,17,43,47,66,76,83,128,146,157,185,208],"low-power":[4,84],"fractional-":[5,158],"":[8,161,177,200],"${N}$":[10,163],"":[11,164,181,204],"all-digital":[12],"phase-locked":[13],"loop":[14],"(ADPLL)":[15],"employing":[16],"reference-waveform":[18],"oversampling":[19,182],"(ROS)":[20],"phase":[21,59],"detector":[22],"(PD)":[23],"that":[24],"increases":[25],"its":[26],"effective":[27],"rate":[28,183],"four":[29],"times,":[30],"thus":[31],"leading":[32],"to":[33,145,167],"lower":[34],"jitter":[35,134],"and":[36,56,80,174],"settling":[37],"time.":[38],"The":[39,69,115,125],"proposed":[40,116,193],"ROS-PD":[41],"adopts":[42],"bottom-plate":[44],"sampling":[45],"with":[46,131],"voltage":[48,63],"zero-forcing":[49],"technique,":[50],"which":[51],"yields":[52],"high":[53],"power":[54],"efficiency":[55],"supports":[57],"fractional":[58,113],"compensation":[60],"in":[61,120,156,205],"the":[62,92,100,168,192],"domain":[64],"through":[65],"programmable":[67],"DAC.":[68],"PD":[70],"output":[71],"is":[72,118],"then":[73],"amplified":[74],"by":[75,82,105],"low-noise":[77],"gated":[78],"amplifier":[79],"digitized":[81],"successive":[85],"approximation":[86],"register":[87],"analog-to-digital":[88],"converter":[89],"(SAR-ADC).":[90],"Leveraging":[91],"benefits":[93],"of":[94,107,135,153,207],"digital":[95],"architecture,":[96],"gain":[97],"mismatches":[98],"from":[99,184],"waveform":[101],"estimator":[102],"are":[103],"calibrated":[104],"means":[106],"an":[108,132],"LMS":[109],"algorithm,":[110],"consequently":[111],"lowering":[112],"spurs.":[114],"ADPLL":[117,148,194],"implemented":[119],"TSMC":[121],"28-nm":[122],"LP":[123],"CMOS.":[124],"prototype":[126],"generates":[127],"2.0\u20132.3-GHz":[129],"carrier":[130],"rms":[133],"414":[136],"fs":[137],"while":[138],"consuming":[139],"only":[140],"1.15":[141],"mW.":[142],"corresponds":[144],"state-of-the-art":[147],"FoM":[149],"jitter":[152],"\u2212247":[154],"dB":[155],"mode.":[165],"Due":[166],"wide":[169],"(largely":[170],"linear)":[171],"monotonic":[172],"range":[173],"notation=\"LaTeX\">$4\\times":[179],"$":[180],"48-MHz":[186],"reference,":[187],"without":[188],"any":[189],"additional":[190],"circuitry,":[191],"can":[195],"settle":[196],"within":[197],"notation=\"LaTeX\">$3~\\mu":[202],"\\text{s}$":[203],"face":[206],"70-MHz":[209],"frequency":[210],"step.":[211]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W3189958273","counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2024-03-22T06:41:09.997286","created_date":"2021-08-16"}