{"id":"https://openalex.org/W3123558452","doi":"https://doi.org/10.1109/jssc.2020.3048726","title":"A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control","display_name":"A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control","publication_year":2021,"publication_date":"2021-01-22","ids":{"openalex":"https://openalex.org/W3123558452","doi":"https://doi.org/10.1109/jssc.2020.3048726","mag":"3123558452"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2020.3048726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.3048726","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009090618","display_name":"Luke Everson","orcid":"https://orcid.org/0000-0002-1209-0395"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Luke R. Everson","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068714995","display_name":"Sachin S. Sapatnekar","orcid":"https://orcid.org/0000-0002-5353-2364"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sachin S. Sapatnekar","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043025421","display_name":"Chris H. Kim","orcid":"https://orcid.org/0000-0002-4194-1347"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris H. Kim","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009090618"],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":0.6725,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.69846405,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"56","issue":"7","first_page":"2281","last_page":"2290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12292","display_name":"Graph Theory and Algorithms","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9861000180244446,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11896","display_name":"Opportunistic and Delay-Tolerant Networks","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6851544380187988},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5939618945121765},{"id":"https://openalex.org/keywords/shortest-path-problem","display_name":"Shortest path problem","score":0.5884023308753967},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5169836282730103},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4961753785610199},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4534606337547302},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.451291561126709},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4398709535598755},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.42809635400772095},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4146740734577179},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.3593151867389679},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3453786373138428},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34306401014328003},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28228873014450073},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24999669194221497},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.16513508558273315},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.136714369058609},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11404553055763245}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6851544380187988},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5939618945121765},{"id":"https://openalex.org/C22590252","wikidata":"https://www.wikidata.org/wiki/Q1058754","display_name":"Shortest path problem","level":3,"score":0.5884023308753967},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5169836282730103},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4961753785610199},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4534606337547302},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.451291561126709},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4398709535598755},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.42809635400772095},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4146740734577179},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3593151867389679},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3453786373138428},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34306401014328003},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28228873014450073},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24999669194221497},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.16513508558273315},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.136714369058609},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11404553055763245},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2020.3048726","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.3048726","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G2696418594","display_name":null,"funder_award_id":"CCF-1763761","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1969483458","https://openalex.org/W1974909294","https://openalex.org/W2153580689","https://openalex.org/W2169528473","https://openalex.org/W2344729295","https://openalex.org/W2508029414","https://openalex.org/W2566870951","https://openalex.org/W2795118915","https://openalex.org/W2921421334","https://openalex.org/W4241140669","https://openalex.org/W6760724420"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2316202402","https://openalex.org/W2074043759","https://openalex.org/W2082487009","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W2154351074"],"abstract_inverted_index":{"A":[0,50],"mixed-signal,":[1],"time-based":[2],"65-nm":[3],"application-specific":[4],"integrated":[5],"circuit":[6],"is":[7,53,59],"developed":[8],"for":[9,76],"solving":[10],"shortest-path":[11],"problems.":[12],"Digital":[13],"circuits":[14],"are":[15,86],"collocated":[16],"with":[17,110,129],"the":[18,37,40,44],"memory":[19],"as":[20,114],"intra-memory":[21],"computing.":[22],"The":[23,94,120],"core":[24,41],"follows":[25],"similar":[26],"principles":[27],"from":[28,55],"wave":[29],"routing":[30],"and,":[31],"additionally,":[32],"incorporates":[33],"a":[34],"gradient":[35],"on":[36],"periphery":[38],"of":[39,133],"to":[42,68,88],"implement":[43],"A*":[45],"algorithm":[46],"predicted":[47],"distance":[48],"heuristic.":[49],"leading":[51],"pulse":[52],"propagated":[54],"start":[56],"nodes":[57],"and":[58,66,82,85,118],"asynchronously":[60],"latched":[61],"in":[62],"neighboring":[63],"vertex":[64],"cells":[65],"pushed":[67],"its":[69],"four":[70],"neighbors.":[71],"Applications":[72],"include":[73],"collision":[74],"avoidance":[75],"self-driving":[77],"cars,":[78],"shortest":[79],"path":[80],"planning,":[81],"scientific":[83],"computing,":[84],"shown":[87],"be":[89],"scalable":[90],"across":[91],"many":[92],"cores.":[93],"chip":[95],"achieves":[96],"559":[97],"million":[98],"traversed":[99],"edges":[100],"per":[101,127],"second":[102],"at":[103,124],"105":[104],"\u00d7":[105],"improved":[106],"energy":[107],"efficiency":[108],"compared":[109],"existing":[111],"platforms":[112],"such":[113],"field-programmable":[115],"gate":[116],"array":[117],"CPU.":[119],"processor":[121],"operates":[122],"nominally":[123],"1.79":[125],"ns":[126],"node":[128],"peak":[130],"power":[131],"consumption":[132],"26.4":[134],"mW.":[135]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
