{"id":"https://openalex.org/W3085612199","doi":"https://doi.org/10.1109/jssc.2020.3021279","title":"A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-<i>N</i> MDLL in 22-nm FinFET CMOS","display_name":"A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-<i>N</i> MDLL in 22-nm FinFET CMOS","publication_year":2020,"publication_date":"2020-09-14","ids":{"openalex":"https://openalex.org/W3085612199","doi":"https://doi.org/10.1109/jssc.2020.3021279","mag":"3085612199"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2020.3021279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.3021279","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078845675","display_name":"Somnath Kundu","orcid":"https://orcid.org/0000-0002-5891-7968"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Somnath Kundu","raw_affiliation_strings":["Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0002-5891-7968","affiliations":[{"raw_affiliation_string":"Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039204143","display_name":"Likai Chai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Likai Chai","raw_affiliation_strings":["Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039602588","display_name":"Kailash Chandrashekar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kailash Chandrashekar","raw_affiliation_strings":["Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065695022","display_name":"Stefano Pellerano","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stefano Pellerano","raw_affiliation_strings":["Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059381050","display_name":"Brent Carlton","orcid":"https://orcid.org/0000-0003-4542-4715"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brent R. Carlton","raw_affiliation_strings":["Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-4542-4715","affiliations":[{"raw_affiliation_string":"Radio Circuits and Technology Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078845675"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.8726,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.86017137,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"56","issue":"1","first_page":"43","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7146671414375305},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.7028181552886963},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6660881638526917},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.5803197622299194},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.5639451146125793},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.5418395400047302},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.49174764752388},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4401651620864868},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4268791377544403},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.42197397351264954},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.30998873710632324},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2822340726852417},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.28151363134384155},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15023335814476013},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14972391724586487},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10621088743209839}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7146671414375305},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.7028181552886963},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6660881638526917},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.5803197622299194},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.5639451146125793},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.5418395400047302},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.49174764752388},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4401651620864868},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4268791377544403},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.42197397351264954},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.30998873710632324},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2822340726852417},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.28151363134384155},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15023335814476013},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14972391724586487},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10621088743209839},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2020.3021279","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.3021279","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1948778041","https://openalex.org/W1989484081","https://openalex.org/W2019720625","https://openalex.org/W2062327827","https://openalex.org/W2066871406","https://openalex.org/W2072473787","https://openalex.org/W2085806603","https://openalex.org/W2086336002","https://openalex.org/W2112008043","https://openalex.org/W2120500930","https://openalex.org/W2121854746","https://openalex.org/W2161139924","https://openalex.org/W2275003682","https://openalex.org/W2516199239","https://openalex.org/W2570002238","https://openalex.org/W2754812974","https://openalex.org/W2790292185","https://openalex.org/W2800181724","https://openalex.org/W2901281781","https://openalex.org/W2966202279","https://openalex.org/W3003987747","https://openalex.org/W3015964844","https://openalex.org/W3081671533","https://openalex.org/W3142120744","https://openalex.org/W6676844732","https://openalex.org/W6776734828"],"related_works":["https://openalex.org/W2283201674","https://openalex.org/W4385412989","https://openalex.org/W2107514446","https://openalex.org/W1988254802","https://openalex.org/W2900936676","https://openalex.org/W2563745415","https://openalex.org/W2558159544","https://openalex.org/W1971399211","https://openalex.org/W2223905331","https://openalex.org/W2152680645"],"abstract_inverted_index":{"This":[0],"article":[1],"describes":[2],"a":[3,87,96,107,125],"synthesized":[4,154],"fractional-N":[5],"multiplying":[6],"delay-locked":[7],"loop":[8,127],"(MDLL)":[9],"implemented":[10],"in":[11,56,91,115,129],"Intel":[12],"22-nm":[13],"FFL":[14],"FinFET":[15],"technology.":[16],"A":[17,43,132],"2-bit":[18,68],"time-period":[19],"comparator":[20],"(TPC)":[21],"is":[22,46,83,122,156,177,195],"proposed":[23,143],"to":[24,30,38,48,104,119,170],"adjust":[25],"the":[26,32,50,53,64,92,99,130,136,142,153,165,181,199],"ring":[27],"oscillator":[28,102],"frequency":[29,166],"suppress":[31],"spurs":[33,182],"without":[34,75],"introducing":[35],"errors":[36],"due":[37,118],"its":[39],"inherent":[40],"phase":[41],"offset.":[42],"programmable":[44],"delay":[45,117],"used":[47],"compare":[49],"periods":[51],"of":[52,98,109,135,141,152,201,204],"MDLL":[54,144,192],"output":[55,69],"time":[57],"domain,":[58],"reducing":[59],"power":[60,193],"consumption":[61,194],"and":[62,72,139,180],"making":[63],"design":[65,155],"synthesizable.":[66],"TPC":[67],"achieves":[70],"fast":[71],"robust":[73],"locking":[74],"any":[76],"initial":[77],"calibration.":[78],"The":[79,149,173],"fractional":[80],"multiplication":[81],"ratio":[82],"achieved":[84],"by":[85,124],"using":[86],"digital-to-time":[88],"converter":[89],"(DTC)":[90],"reference":[93],"path":[94],"with":[95,198],"replica":[97],"digitally":[100],"controlled":[101],"(DCO)":[103],"automatically":[105],"achieve":[106],"range":[108,167],"one":[110],"DCO":[111],"period.":[112],"Any":[113],"variation":[114],"DTC":[116],"gain":[120],"mismatch":[121],"corrected":[123],"digital":[126],"operating":[128,163],"background.":[131],"detailed":[133],"analysis":[134],"small-signal":[137],"model":[138],"noise":[140],"has":[145],"also":[146],"been":[147],"presented.":[148],"core":[150],"area":[151],"0.0052":[157],"mm":[158],"<sup":[159],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[160],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[161],"while":[162],"over":[164],"from":[168],"1.2":[169],"3.8":[171],"GHz.":[172,190],"integrated":[174],"rms":[175],"jitter":[176],"2.74":[178],"ps,":[179],"are":[183],"below":[184],"-47":[185],"dBc":[186],"measured":[187],"at":[188],"3.6175":[189],"Fractional-N":[191],"3.19":[196],"mW":[197],"figure":[200],"merit":[202],"(FOM)":[203],"-226.3":[205],"dB.":[206]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}