{"id":"https://openalex.org/W3013556183","doi":"https://doi.org/10.1109/jssc.2020.2978384","title":"A 100-MHz BW 72.6-dB-SNDR CT \u0394 \u03a3 Modulator Utilizing Preliminary Sampling and Quantization","display_name":"A 100-MHz BW 72.6-dB-SNDR CT \u0394 \u03a3 Modulator Utilizing Preliminary Sampling and Quantization","publication_year":2020,"publication_date":"2020-01-01","ids":{"openalex":"https://openalex.org/W3013556183","doi":"https://doi.org/10.1109/jssc.2020.2978384","mag":"3013556183"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2020.2978384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.2978384","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032603201","display_name":"Wei Wang","orcid":"https://orcid.org/0000-0001-5804-0230"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Wei Wang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0001-5804-0230","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035229843","display_name":"Chi\u2010Hang Chan","orcid":"https://orcid.org/0000-0002-7635-1101"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Chi-Hang Chan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0002-7635-1101","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071933088","display_name":"Yan Zhu","orcid":"https://orcid.org/0000-0002-8298-3244"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Yan Zhu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0002-8298-3244","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]}],"countries":["CN","MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","Instituto Superior T\u00e9cnico, Universidade de Lisbon, Lisbon, Portugal","Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I4387152517"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2045,"currency":"USD","value_usd":2045},"apc_paid":null,"fwci":0.4531,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.54974053,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11472","display_name":"Analytical Chemistry and Sensors","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1502","display_name":"Bioengineering"},"field":{"id":"https://openalex.org/fields/15","display_name":"Chemical Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.8224201798439026},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.7657896280288696},{"id":"https://openalex.org/keywords/cascade","display_name":"Cascade","score":0.6103938221931458},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.6006958484649658},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.5784579515457153},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.5672376751899719},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5324892401695251},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5311844348907471},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.5047775506973267},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5009901523590088},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4673004150390625},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4128764271736145},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39847251772880554},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32433319091796875},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23808729648590088},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.183295339345932},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15690985321998596}],"concepts":[{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.8224201798439026},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.7657896280288696},{"id":"https://openalex.org/C34146451","wikidata":"https://www.wikidata.org/wiki/Q5048094","display_name":"Cascade","level":2,"score":0.6103938221931458},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.6006958484649658},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.5784579515457153},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.5672376751899719},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5324892401695251},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5311844348907471},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.5047775506973267},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5009901523590088},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4673004150390625},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4128764271736145},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39847251772880554},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32433319091796875},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23808729648590088},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.183295339345932},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15690985321998596},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2020.2978384","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2020.2978384","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1524535447","https://openalex.org/W1984736382","https://openalex.org/W2016095563","https://openalex.org/W2048500522","https://openalex.org/W2057788459","https://openalex.org/W2136429521","https://openalex.org/W2172010302","https://openalex.org/W2177450745","https://openalex.org/W2243588167","https://openalex.org/W2293521946","https://openalex.org/W2398049675","https://openalex.org/W2435810003","https://openalex.org/W2503582469","https://openalex.org/W2513879943","https://openalex.org/W2564508492","https://openalex.org/W2750703890","https://openalex.org/W2778668131","https://openalex.org/W2883559415","https://openalex.org/W2921756781","https://openalex.org/W4255407283","https://openalex.org/W6760674879"],"related_works":["https://openalex.org/W2040229502","https://openalex.org/W1580014081","https://openalex.org/W1523707702","https://openalex.org/W2421111280","https://openalex.org/W2097165798","https://openalex.org/W1497881430","https://openalex.org/W2599174517","https://openalex.org/W2117483815","https://openalex.org/W2157118673","https://openalex.org/W2542642610"],"abstract_inverted_index":{"This":[0],"article":[1],"reports":[2],"a":[3,26,48,102,134,161,168],"4th-order":[4],"100-MHz":[5],"bandwidth":[6,136],"continuous-time":[7],"(CT)":[8],"delta-sigma":[9],"modulator":[10,132],"in":[11,107,117,128],"28-nm":[12],"CMOS.":[13],"A":[14],"preliminary":[15],"sampling":[16,60],"and":[17,61,73,143,154,167],"quantization":[18,35,62],"(PSQ)":[19],"technique":[20],"is":[21,126],"presented,":[22],"which":[23],"allows":[24],"almost":[25],"full":[27],"utilization":[28],"of":[29,42,63,110,112,115,137,164,171,178],"the":[30,34,38,43,56,59,64,77,108,113],"clock":[31],"period":[32],"for":[33],"to":[36,76,80],"extend":[37],"available":[39],"conversion":[40],"time":[41],"backend":[44,65],"quantizer":[45],"(QTZ)":[46],"under":[47],"0.65":[49],"excess":[50],"loop":[51],"delay":[52],"(ELD)":[53],"coefficient.":[54],"With":[55],"PSQ,":[57],"both":[58],"QTZ":[66,84],"are":[67],"splitted":[68],"into":[69],"two":[70],"steps,":[71],"coarse":[72],"fine,":[74],"similar":[75],"subranging":[78],"architecture":[79],"save":[81],"power.":[82,99],"The":[83,131,158],"runs":[85],"at":[86],"2":[87],"GHz":[88],"achieving":[89],"7":[90],"bit":[91],"(1":[92],"b":[93],"error":[94],"correction)":[95],"with":[96,140,174],"only":[97,121,148],"1.4-mW":[98],"By":[100],"adding":[101],"feedforward":[103,118],"ELD":[104],"compensation":[105],"path":[106],"cascade":[109,114],"integrators":[111,116],"(CIFF)":[119],"topology,":[120],"one":[122],"digital-to-analog":[123],"converter":[124],"(DAC)":[125],"necessary":[127],"this":[129],"design.":[130],"attains":[133],"signal":[135],"100":[138],"MHz":[139],"72.6-dB":[141],"signal-to-noise":[142],"distortion":[144],"ratio":[145],"(SNDR)":[146],"while":[147],"consuming":[149],"16.3":[150],"mW":[151],"from":[152],"1.1-":[153],"1.5-V":[155],"power":[156],"supplies.":[157],"prototype":[159],"has":[160],"dynamic":[162],"range":[163],"76.3":[165],"dB":[166,173],"Schreier":[169],"FoM":[170],"174.2":[172],"an":[175],"active":[176],"area":[177],"0.019":[179],"mm2.":[180]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":7},{"year":2023,"cited_by_count":4},{"year":2021,"cited_by_count":2}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}