{"id":"https://openalex.org/W2979367443","doi":"https://doi.org/10.1109/jssc.2019.2942359","title":"A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance","display_name":"A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance","publication_year":2019,"publication_date":"2019-10-08","ids":{"openalex":"https://openalex.org/W2979367443","doi":"https://doi.org/10.1109/jssc.2019.2942359","mag":"2979367443"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2019.2942359","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2019.2942359","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007420130","display_name":"Liang Qi","orcid":"https://orcid.org/0000-0002-9512-4529"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":true,"raw_author_name":"Liang Qi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-9512-4529","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034290581","display_name":"Ankesh Jain","orcid":"https://orcid.org/0000-0003-4109-6312"},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ankesh Jain","raw_affiliation_strings":["Electrical Engineering Department, IIT Delhi, New Delhi, India"],"raw_orcid":"https://orcid.org/0000-0003-4109-6312","affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, IIT Delhi, New Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027487757","display_name":"Dongyang Jiang","orcid":"https://orcid.org/0000-0002-1248-6859"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Dongyang Jiang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-1248-6859","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073702117","display_name":"Sai\u2010Weng Sin","orcid":"https://orcid.org/0000-0001-9346-8291"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Sai-Weng Sin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0001-9346-8291","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Macau, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, Faculty of Science and Technology, Macau, China","Instituto SuperiorT\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Macau, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, Faculty of Science and Technology, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]},{"raw_affiliation_string":"Instituto SuperiorT\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034938079","display_name":"Maurits Ortmanns","orcid":"https://orcid.org/0000-0002-3547-1596"},"institutions":[{"id":"https://openalex.org/I196349391","display_name":"Universit\u00e4t Ulm","ror":"https://ror.org/032000t02","country_code":"DE","type":"education","lineage":["https://openalex.org/I196349391"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Maurits Ortmanns","raw_affiliation_strings":["Faculty of Engineering, Computer Science and Psychology, Institute of Microelectronics, University of Ulm, Ulm, Germany"],"raw_orcid":"https://orcid.org/0000-0002-3547-1596","affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Computer Science and Psychology, Institute of Microelectronics, University of Ulm, Ulm, Germany","institution_ids":["https://openalex.org/I196349391"]}]}],"institutions":[],"countries_distinct_count":5,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5007420130"],"corresponding_institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"],"apc_list":null,"apc_paid":null,"fwci":2.6917,"has_fulltext":false,"cited_by_count":66,"citation_normalized_percentile":{"value":0.9012426,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"55","issue":"2","first_page":"344","last_page":"355"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.8998845815658569},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.6472808122634888},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.6037593483924866},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.5954121351242065},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.5704542398452759},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.568229079246521},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5598548054695129},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4745895564556122},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4307302236557007},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.36671575903892517},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3294776976108551},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32906657457351685},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28212493658065796},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22979941964149475},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.07636725902557373}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.8998845815658569},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.6472808122634888},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.6037593483924866},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.5954121351242065},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.5704542398452759},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.568229079246521},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5598548054695129},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4745895564556122},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4307302236557007},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.36671575903892517},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3294776976108551},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32906657457351685},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28212493658065796},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22979941964149475},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.07636725902557373}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2019.2942359","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2019.2942359","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.49000000953674316}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321655","display_name":"Science and Technology Development Fund","ror":"https://ror.org/044vr6g03"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1485439058","https://openalex.org/W1855267619","https://openalex.org/W1981271965","https://openalex.org/W2014773819","https://openalex.org/W2016095563","https://openalex.org/W2105551738","https://openalex.org/W2107516488","https://openalex.org/W2111878962","https://openalex.org/W2118169469","https://openalex.org/W2121130638","https://openalex.org/W2243588167","https://openalex.org/W2321419239","https://openalex.org/W2503582469","https://openalex.org/W2513879943","https://openalex.org/W2556510987","https://openalex.org/W2559685583","https://openalex.org/W2564508492","https://openalex.org/W2607531354","https://openalex.org/W2752340009","https://openalex.org/W2776359478","https://openalex.org/W2780413837","https://openalex.org/W2909134018"],"related_works":["https://openalex.org/W2005714378","https://openalex.org/W2124911477","https://openalex.org/W2102815341","https://openalex.org/W2128664218","https://openalex.org/W2143648845","https://openalex.org/W2159595243","https://openalex.org/W1991579521","https://openalex.org/W2124502750","https://openalex.org/W2542642610","https://openalex.org/W2101760577"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,56,100,108,117,141],"dual-loop":[4],"noise-coupling":[5],"(NC)-assisted":[6],"continuous-time":[7],"(CT)":[8],"sturdy":[9],"multistage":[10],"noise-shaping":[11],"(SMASH)":[12],"\u0394\u03a3":[13],"modulator":[14],"(DSM),":[15],"employing":[16],"1.5-bit/4-bit":[17],"quantizers.":[18],"The":[19,34],"proposed":[20],"SMASH":[21,40],"can":[22],"equivalently":[23],"work":[24],"as":[25],"an":[26,129],"overall":[27],"fourth-order":[28],"DSM":[29,41],"with":[30],"4-bit":[31],"internal":[32],"quantization.":[33],"NC":[35],"applied":[36],"in":[37],"this":[38],"CT":[39],"whitens":[42],"the":[43,63,68,74,87,94],"1.5-bit":[44],"quantization":[45],"noise":[46,71],"(QN)":[47],"and":[48,107,127],"further":[49],"reduces":[50],"its":[51],"in-band":[52],"tone":[53],"power,":[54],"while":[55],"finite-impulse":[57],"response":[58],"(FIR)":[59],"filter":[60],"integrated":[61],"into":[62],"outermost":[64],"feedback":[65],"path":[66],"suppresses":[67],"out-of-band":[69],"(OOB)":[70],"power":[72],"of":[73,104,113,132,146],"multibit":[75,88],"digital-to-analog":[76],"converter":[77],"(DAC)":[78],"input.":[79],"Together,":[80],"they":[81],"avoid":[82],"any":[83],"linearization":[84],"technique":[85],"for":[86],"DAC.":[89],"Sampled":[90],"at":[91],"1.2":[92],"GHz,":[93],"28-nm":[95],"CMOS":[96],"experimental":[97],"prototype":[98],"measures":[99],"signal-to-noise-and-distortion":[101],"ratio":[102],"(SNDR)":[103,145],"76.6":[105],"dB":[106,115],"spurious-free":[109],"dynamic":[110],"range":[111],"(SFDR)":[112],"87.9":[114],"over":[116],"50-MHz":[118],"bandwidth":[119],"(BW),":[120],"consuming":[121],"29.2":[122],"mW":[123],"from":[124],"1.2-V/1.5-V":[125],"supplies":[126],"occupying":[128],"active":[130],"area":[131],"0.085":[133],"mm":[134],"<sup":[135],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[136],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[137],".":[138],"It":[139],"exhibits":[140],"Schreier":[142],"figure-of-merit":[143],"(FoM)":[144],"168.9":[147],"dB.":[148]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":10},{"year":2021,"cited_by_count":13},{"year":2020,"cited_by_count":4}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}