{"id":"https://openalex.org/W4229595843","doi":"https://doi.org/10.1109/jssc.2019.2941259","title":"A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power","display_name":"A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power","publication_year":2019,"publication_date":"2019-10-03","ids":{"openalex":"https://openalex.org/W4229595843","doi":"https://doi.org/10.1109/jssc.2019.2941259"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2019.2941259","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2019.2941259","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075806913","display_name":"Alessio Santiccioli","orcid":"https://orcid.org/0000-0002-2301-5702"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessio Santiccioli","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":"https://orcid.org/0000-0002-2301-5702","affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027695549","display_name":"Mario Mercandelli","orcid":"https://orcid.org/0000-0003-0847-9207"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario Mercandelli","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":"https://orcid.org/0000-0003-0847-9207","affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051946676","display_name":"Andrea L. Lacaita","orcid":"https://orcid.org/0000-0003-0315-514X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea L. Lacaita","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":"https://orcid.org/0000-0003-0315-514X","affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073514694","display_name":"Carlo Samori","orcid":"https://orcid.org/0000-0002-7084-0721"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Carlo Samori","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085904857","display_name":"Salvatore Levantino","orcid":"https://orcid.org/0000-0003-0895-1700"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Salvatore Levantino","raw_affiliation_strings":["Politecnico di Milano, Milan, Italy"],"raw_orcid":"https://orcid.org/0000-0003-0895-1700","affiliations":[{"raw_affiliation_string":"Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I93860229"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":2.4178,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.89415369,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"54","issue":"11","first_page":"3149","last_page":"3160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9358168840408325},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6479150056838989},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5417623519897461},{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.5138976573944092},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.509963870048523},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.5064879655838013},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.49502629041671753},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.49447202682495117},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4646996855735779},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.44945967197418213},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.42310696840286255},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3929747939109802},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37306690216064453},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2129620909690857},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19338557124137878},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1922067105770111},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.13277506828308105}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9358168840408325},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6479150056838989},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5417623519897461},{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.5138976573944092},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.509963870048523},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.5064879655838013},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.49502629041671753},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.49447202682495117},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4646996855735779},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.44945967197418213},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.42310696840286255},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3929747939109802},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37306690216064453},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2129620909690857},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19338557124137878},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1922067105770111},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.13277506828308105},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/jssc.2019.2941259","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2019.2941259","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1112456","is_oa":false,"landing_page_url":"http://hdl.handle.net/11311/1112456","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1970092416","https://openalex.org/W1975693956","https://openalex.org/W1989484081","https://openalex.org/W2001782539","https://openalex.org/W2066871406","https://openalex.org/W2102596261","https://openalex.org/W2107514446","https://openalex.org/W2108324407","https://openalex.org/W2119816915","https://openalex.org/W2121854746","https://openalex.org/W2151100180","https://openalex.org/W2290934758","https://openalex.org/W2291102602","https://openalex.org/W2291605840","https://openalex.org/W2538722267","https://openalex.org/W2577476579","https://openalex.org/W2605666562","https://openalex.org/W2736004295","https://openalex.org/W2790060412","https://openalex.org/W2800181724","https://openalex.org/W2948830776","https://openalex.org/W3209783674","https://openalex.org/W4229595843","https://openalex.org/W6644280247","https://openalex.org/W6677805037","https://openalex.org/W6697021775","https://openalex.org/W6751015320","https://openalex.org/W6803556542"],"related_works":["https://openalex.org/W2766503024","https://openalex.org/W4206637278","https://openalex.org/W2781247653","https://openalex.org/W4386005305","https://openalex.org/W3082051559","https://openalex.org/W1682621979","https://openalex.org/W4386214543","https://openalex.org/W2139484866","https://openalex.org/W2198645257","https://openalex.org/W67296738"],"abstract_inverted_index":{"This":[0],"article":[1],"analyzes":[2],"the":[3,14,50,54,114],"jitter-power":[4,97],"tradeoff":[5],"in":[6,67],"multiplying":[7],"delay-locked":[8],"loops":[9],"(MDLLs),":[10],"which":[11,48],"differs":[12],"from":[13,82],"more":[15],"typical":[16],"phase-locked":[17],"loop":[18],"one,":[19],"and":[20,40,70,113],"identifies":[21],"a":[22,31,35,41,72,95],"design":[23],"optimization":[24],"criterion.":[25],"The":[26,62],"methodology":[27],"is":[28,118],"applied":[29],"to":[30,53,85],"fractional-N":[32],"MDLL":[33],"with":[34,94],"sub-sampling":[36],"bang-bang":[37],"phase":[38],"detector":[39],"novel":[42],"digital-to-time":[43],"converter":[44],"(DTC)":[45],"range-reduction":[46],"technique,":[47],"limits":[49],"jitter":[51,80],"added":[52],"reference":[55],"signal,":[56],"at":[57,91],"no":[58],"additional":[59],"power":[60],"penalty.":[61],"prototype":[63],"has":[64],"been":[65],"implemented":[66],"65-nm":[68],"CMOS":[69],"covers":[71],"1.6-to-3.0-GHz":[73],"tuning":[74],"range,":[75],"achieving":[76],"an":[77],"absolute":[78],"rms":[79],"(integrated":[81],"30":[83,86],"kHz":[84],"MHz)":[87],"of":[88,99,101],"397":[89],"fs":[90],"2.5-mW":[92],"power,":[93],"corresponding":[96],"figure":[98],"merit":[100],"-244":[102],"dB.":[103],"In-band":[104],"fractional":[105],"spurs":[106],"are":[107],"as":[108,110],"low":[109],"-51.5":[111],"dB":[112],"occupied":[115],"core":[116],"area":[117],"0.0275":[119],"mm2.":[120]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":14},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}