{"id":"https://openalex.org/W2728034738","doi":"https://doi.org/10.1109/jssc.2017.2715160","title":"Fractional-N DPLL-Based Low-Power Clocking Architecture for 1\u201314 Gb/s Multi-Standard Transmitter","display_name":"Fractional-N DPLL-Based Low-Power Clocking Architecture for 1\u201314 Gb/s Multi-Standard Transmitter","publication_year":2017,"publication_date":"2017-07-06","ids":{"openalex":"https://openalex.org/W2728034738","doi":"https://doi.org/10.1109/jssc.2017.2715160","mag":"2728034738"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2017.2715160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2017.2715160","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084099546","display_name":"Masum Hossain","orcid":"https://orcid.org/0000-0002-4118-9212"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Masum Hossain","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058593138","display_name":"Waleed El-Halwagy","orcid":"https://orcid.org/0000-0001-7666-4004"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Waleed El-Halwagy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050103474","display_name":"AKM Delwar Hossain","orcid":"https://orcid.org/0000-0002-3765-9672"},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"AKM Delwar Hossain","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056199839","display_name":"Fnu Aurangozeb","orcid":null},"institutions":[{"id":"https://openalex.org/I154425047","display_name":"University of Alberta","ror":"https://ror.org/0160cpw27","country_code":"CA","type":"education","lineage":["https://openalex.org/I154425047"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Aurangozeb","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada"],"raw_orcid":"https://orcid.org/0000-0002-6159-9067","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada","institution_ids":["https://openalex.org/I154425047"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7309,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.73138084,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"52","issue":"10","first_page":"2647","last_page":"2662"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9882000088691711,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9254738092422485},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8415689468383789},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.6964573264122009},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.6286695003509521},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.5920470952987671},{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.5846167206764221},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5025336742401123},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47721701860427856},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47540292143821716},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.4130447208881378},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4041503071784973},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34390121698379517},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.26118698716163635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25301456451416016}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9254738092422485},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8415689468383789},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.6964573264122009},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6286695003509521},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.5920470952987671},{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.5846167206764221},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5025336742401123},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47721701860427856},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47540292143821716},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.4130447208881378},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4041503071784973},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34390121698379517},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.26118698716163635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25301456451416016},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2017.2715160","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2017.2715160","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2023401960","https://openalex.org/W2035526941","https://openalex.org/W2094264485","https://openalex.org/W2105386586","https://openalex.org/W2120500930","https://openalex.org/W2131053965","https://openalex.org/W2144581882","https://openalex.org/W2146606114","https://openalex.org/W2166984288","https://openalex.org/W2170296279","https://openalex.org/W2179481090","https://openalex.org/W2587314600","https://openalex.org/W3142120744","https://openalex.org/W6681887207"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W1487557653","https://openalex.org/W2103754166","https://openalex.org/W2058003010","https://openalex.org/W2376275105","https://openalex.org/W2899351227","https://openalex.org/W2350523680","https://openalex.org/W2757255852"],"abstract_inverted_index":{"A":[0],"low-power":[1],"clocking":[2],"solution":[3],"is":[4,57,63],"presented":[5],"based":[6],"on":[7],"fractional-N":[8,24],"highly":[9],"digital":[10,25],"LC-phase-locked":[11],"loop":[12],"(PLL)":[13],"and":[14,36,83,102],"sub-sampled":[15],"ring":[16,68,87],"PLL":[17,69,88],"targeting":[18],"multi-standard":[19],"SerDes":[20],"applications.":[21],"The":[22,86],"shared":[23],"LC-PLL":[26,56],"covers":[27],"7-10":[28],"GHz":[29,75],"frequency":[30],"range":[31],"consuming":[32],"only":[33],"8-mW":[34],"power":[35,115],"occupying":[37],"0.15":[38],"mm":[39],"<sup":[40],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[41],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[42],"of":[43,49,54,93,117],"silicon":[44],"area":[45],"with":[46,99,114],"integrated":[47,107],"jitter":[48],"264":[50],"fs.":[51],"Frequency":[52],"resolution":[53,92],"the":[55,78],"2":[58],"MHz.":[59],"Per":[60],"lane":[61],"clock":[62],"generated":[64],"using":[65],"wide":[66],"bandwidth":[67],"covering":[70],"800":[71],"MHz":[72],"to":[73,76],"4":[74],"support":[77],"data":[79],"rates":[80],"between":[81],"1":[82],"14":[84,112],"Gb/s.":[85],"supports":[89],"dither-less":[90],"fractional":[91],"250":[94],"MHz,":[95],"corrects":[96],"I/Q":[97],"error":[98],"split":[100],"tuning,":[101],"achieves":[103],"less":[104],"than":[105],"400-fs":[106],"jitter.":[108],"Transmitter":[109],"works":[110],"at":[111],"Gb/s":[113],"efficiency":[116],"0.80":[118],"pJ/bit.":[119]},"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}