{"id":"https://openalex.org/W2580334840","doi":"https://doi.org/10.1109/jssc.2016.2636859","title":"A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS","display_name":"A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS","publication_year":2017,"publication_date":"2017-01-23","ids":{"openalex":"https://openalex.org/W2580334840","doi":"https://doi.org/10.1109/jssc.2016.2636859","mag":"2580334840"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2016.2636859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2636859","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075692568","display_name":"Sudhir Satpathy","orcid":"https://orcid.org/0000-0003-3511-3526"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhir Satpathy","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0003-3511-3526","affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu K. Mathew","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078003656","display_name":"Vikram Suresh","orcid":"https://orcid.org/0000-0001-8879-1967"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vikram Suresh","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark A. Anders","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081032347","display_name":"Himanshu Kaul","orcid":"https://orcid.org/0000-0003-1586-7486"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Amit Agarwal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109275074","display_name":"Steven K. Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven K. Hsu","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090166397","display_name":"Gregory Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory Chen","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram K. Krishnamurthy","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek K. De","raw_affiliation_strings":["Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":11.0979,"has_fulltext":false,"cited_by_count":113,"citation_normalized_percentile":{"value":0.99124827,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"52","issue":"4","first_page":"940","last_page":"949"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9851999878883362,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/physical-unclonable-function","display_name":"Physical unclonable function","score":0.7160412073135376},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6803203225135803},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5364482998847961},{"id":"https://openalex.org/keywords/key-generation","display_name":"Key generation","score":0.5181230902671814},{"id":"https://openalex.org/keywords/bch-code","display_name":"BCH code","score":0.4335959255695343},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.42424729466438293},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3654007315635681},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.336132287979126},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3111332654953003},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.30017632246017456},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.29464370012283325},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19800525903701782}],"concepts":[{"id":"https://openalex.org/C8643368","wikidata":"https://www.wikidata.org/wiki/Q4046262","display_name":"Physical unclonable function","level":3,"score":0.7160412073135376},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6803203225135803},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5364482998847961},{"id":"https://openalex.org/C163173736","wikidata":"https://www.wikidata.org/wiki/Q3308558","display_name":"Key generation","level":3,"score":0.5181230902671814},{"id":"https://openalex.org/C42276685","wikidata":"https://www.wikidata.org/wiki/Q795705","display_name":"BCH code","level":3,"score":0.4335959255695343},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.42424729466438293},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3654007315635681},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.336132287979126},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3111332654953003},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.30017632246017456},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.29464370012283325},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19800525903701782}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2016.2636859","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2636859","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1511514754","https://openalex.org/W1584496665","https://openalex.org/W1785085096","https://openalex.org/W1967501125","https://openalex.org/W1971935236","https://openalex.org/W1981555606","https://openalex.org/W2001067488","https://openalex.org/W2017174041","https://openalex.org/W2017500042","https://openalex.org/W2046467839","https://openalex.org/W2053877171","https://openalex.org/W2057279554","https://openalex.org/W2067907366","https://openalex.org/W2094192676","https://openalex.org/W2095526927","https://openalex.org/W2102576814","https://openalex.org/W2106839704","https://openalex.org/W2117322103","https://openalex.org/W2120317475","https://openalex.org/W2130351941","https://openalex.org/W2149648080","https://openalex.org/W2151715374","https://openalex.org/W2151759197","https://openalex.org/W2290692811","https://openalex.org/W2526479254","https://openalex.org/W4237236484","https://openalex.org/W6638129301","https://openalex.org/W6643323797","https://openalex.org/W6679357471"],"related_works":["https://openalex.org/W4390606075","https://openalex.org/W3209932692","https://openalex.org/W2739747457","https://openalex.org/W2976888033","https://openalex.org/W2150843699","https://openalex.org/W2971795314","https://openalex.org/W4387129757","https://openalex.org/W2971718024","https://openalex.org/W2898201669","https://openalex.org/W4311263387"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,11],"full-entropy":[4,83],"128-b":[5,84],"key":[6,85,138,146],"generation":[7,139,147],"platform":[8],"based":[9],"on":[10],"1024-b":[12],"hybrid":[13,26],"physically":[14],"unclonable":[15],"function":[16],"(PUF)":[17],"array,":[18],"fabricated":[19],"in":[20,38,76,136],"14-nm":[21],"trigate":[22],"high-k/metal-gate":[23],"CMOS.":[24],"Delay-hardened":[25],"PUF":[27,67,93,108,173],"cells":[28],"use":[29],"differential":[30],"clock":[31,197],"delay":[32],"insertion":[33],"to":[34,65,73,182,190],"favor":[35],"circuit":[36],"evaluation":[37,206],"the":[39,90],"desired":[40],"direction":[41],"while":[42],"leveraging":[43,179],"burn-in-induced":[44],"aging":[45,177],"for":[46],"selective":[47],"bit":[48,68],"destabilization":[49],"enabling":[50],"quick":[51],"identification":[52],"and":[53,58,99,151,168,187,207],"masking":[54,64],"of":[55,132],"unstable":[56],"cells,":[57],"subsequent":[59],"temporal-majority-voting":[60],"with":[61,106,121,144,161,175,194],"soft":[62],"dark-bit":[63],"reduce":[66],"error":[69,97],"by":[70,178],"3.9":[71],"times":[72,155],"1.45%":[74],"resulting":[75,135],"~5":[77],"ppb":[78],"failure":[79],"probability.":[80],"A":[81],"stable":[82,145],"is":[86],"finally":[87],"generated":[88],"from":[89,200],"1024":[91],"raw":[92],"bits":[94],"using":[95],"BCH":[96],"correction":[98],"AES-CBC-based":[100],"entropy":[101,163],"extraction.":[102],"An":[103],"all-digital":[104],"design":[105],"compact":[107],"cell":[109,185],"layout":[110],"occupying":[111],"1.84":[112],"\u03bcm":[113],"<sup":[114],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[115],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[116],"achieves:":[117],"1)":[118],"4-fJ/b":[119],"energy-efficiency":[120],"3-\u03bcW":[122],"leakage":[123],"at":[124],"0.65":[125],"V,":[126,150],"70\u00b0C;":[127],"2)":[128],"peak":[129],"operating":[130],"frequency":[131],"1":[133],"GHz":[134],"1.2-\u03bcs":[137],"latency;":[140],"3)":[141],"robust":[142],"operation":[143],"across":[148],"0.55-0.75":[149],"25\u00b0C-110\u00b0C;":[152],"4)":[153],"14":[154],"separation":[156],"between":[157,204],"intra/inter-PUF":[158],"hamming":[159,202],"distances":[160],"0.99993":[162],"ensuring":[164],"cryptographic":[165],"quality":[166],"randomness":[167],"uniqueness;":[169],"5)":[170],"48%":[171],"higher":[172],"stability":[174],"long-term":[176],"transistor":[180],"degradation":[181],"reinforce":[183],"favorable":[184],"bias;":[186],"6)":[188],"resiliency":[189],"power":[191],"cycling":[192],"attacks":[193],"common":[195],"centroid":[196],"routing":[198],"measured":[199],"49.5%":[201],"distance":[203],"array's":[205],"wake-up":[208],"states.":[209]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":12},{"year":2024,"cited_by_count":12},{"year":2023,"cited_by_count":16},{"year":2022,"cited_by_count":14},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":23},{"year":2019,"cited_by_count":18},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
