{"id":"https://openalex.org/W2524971917","doi":"https://doi.org/10.1109/jssc.2016.2607219","title":"5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology","display_name":"5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology","publication_year":2016,"publication_date":"2016-09-29","ids":{"openalex":"https://openalex.org/W2524971917","doi":"https://doi.org/10.1109/jssc.2016.2607219","mag":"2524971917"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2016.2607219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2607219","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003048953","display_name":"Jaydeep P. Kulkarni","orcid":"https://orcid.org/0000-0002-0258-6776"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaydeep P. Kulkarni","raw_affiliation_strings":["Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0000-0002-0258-6776","affiliations":[{"raw_affiliation_string":"Circuit Research Lab, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102812519","display_name":"John Keane","orcid":"https://orcid.org/0000-0002-9746-8990"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Keane","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070089019","display_name":"Kyung-Hoae Koo","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kyung-Hoae Koo","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050071437","display_name":"Satyanand Nalam","orcid":"https://orcid.org/0000-0002-6767-1752"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satyanand Nalam","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007891380","display_name":"Zheng Guo","orcid":"https://orcid.org/0000-0001-8615-9749"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Guo","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053857493","display_name":"Eric Karl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eric Karl","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":null,"display_name":"Kevin Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhang","raw_affiliation_strings":["Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Design Group, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.4937,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.89516779,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"52","issue":"1","first_page":"229","last_page":"239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8114719390869141},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6411608457565308},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.6137521266937256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5186447501182556},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5173817873001099},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5170589089393616},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4778535068035126},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.45545995235443115},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.45315149426460266},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.43502703309059143},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4342012107372284},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.41478264331817627},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3763282895088196},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3531203269958496},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3362593650817871},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19135838747024536},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.187942773103714},{"id":"https://openalex.org/keywords/electrode","display_name":"Electrode","score":0.18202504515647888}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8114719390869141},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6411608457565308},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.6137521266937256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5186447501182556},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5173817873001099},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5170589089393616},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4778535068035126},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.45545995235443115},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.45315149426460266},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.43502703309059143},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4342012107372284},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.41478264331817627},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3763282895088196},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3531203269958496},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3362593650817871},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19135838747024536},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.187942773103714},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.18202504515647888},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2016.2607219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2607219","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6299999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1488734054","https://openalex.org/W1979684454","https://openalex.org/W1990687242","https://openalex.org/W1998377849","https://openalex.org/W2014993833","https://openalex.org/W2170109093","https://openalex.org/W2288931810","https://openalex.org/W2797781943","https://openalex.org/W3144413718","https://openalex.org/W6648162073","https://openalex.org/W6696294842","https://openalex.org/W6750678478"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2373152541","https://openalex.org/W2174410816","https://openalex.org/W3200702775","https://openalex.org/W3209598999","https://openalex.org/W2159817233","https://openalex.org/W2351439697","https://openalex.org/W3010128671"],"abstract_inverted_index":{"Multiported":[0],"high-performance":[1],"on-die":[2],"memories":[3],"occupy":[4],"significantly":[5],"more":[6],"die":[7],"area":[8],"than":[9],"a":[10,32,53,149,156,193],"comparable":[11],"single-port":[12],"memory.":[13],"Among":[14],"various":[15],"multiport":[16],"memory":[17],"topologies,":[18],"the":[19,40,75,92,108,162,170,182,188,197,206],"1-read":[20],"(R),":[21],"1-write":[22],"(W)":[23],"8-transistor":[24],"(T)":[25],"Static":[26],"Random":[27],"Access":[28],"Memory":[29],"(SRAM)":[30],"with":[31,60],"decoupled":[33],"read":[34,41,69,94,98,183],"port":[35],"allows":[36],"separate":[37],"optimization":[38],"of":[39,138,164],"and":[42,71,196,219],"write":[43,72],"ports":[44,66],"when":[45],"organized":[46],"without":[47],"interleaved":[48],"logical":[49],"columns.":[50],"This":[51,96],"enables":[52],"lower":[54],"minimum":[55],"operating":[56],"voltage":[57,158,195],"(Vmin)":[58],"compared":[59],"other":[61],"dual-port":[62],"SRAMs":[63],"that":[64],"require":[65],"optimized":[67],"for":[68,122],"stability":[70],"operations.":[73],"However,":[74],"1R1W":[76],"8T":[77,134],"SRAM":[78,135],"often":[79],"employs":[80,148],"large":[81],"signal,":[82],"hierarchical":[83],"bitline":[84,104,131,184,199],"sensing":[85,105,125],"to":[86,91,126,154,186,204],"achieve":[87],"high":[88],"performance":[89],"due":[90],"nondifferential":[93],"bitline.":[95],"large-signal":[97],"architecture":[99],"necessitates":[100],"frequently":[101],"placed":[102],"local":[103],"circuits,":[106],"degrading":[107],"array":[109,136],"bit":[110],"density.":[111],"In":[112],"this":[113],"paper,":[114],"we":[115],"present":[116],"two":[117],"sense":[118],"amplifier":[119],"(SA)":[120],"techniques":[121],"small-signal":[123],"pseudodifferential":[124],"facilitate":[127],"256":[128],"bits":[129],"per":[130],"achieving":[132],"an":[133,177],"density":[137],"5.6":[139],"Mb/mm2in":[140],"14":[141],"nm":[142],"FinFET":[143],"CMOS.":[144],"The":[145,173],"first":[146],"design":[147,175],"charge":[150],"sharing":[151],"SA":[152,179],"scheme":[153],"generate":[155],"reference":[157,194],"(VREF)":[159],"by":[160],"leveraging":[161],"capacitance":[163],"otherwise":[165],"unused":[166],"metal":[167],"tracks":[168],"over":[169],"bitcell":[171],"column.":[172],"second":[174],"utilizes":[176],"asymmetric":[178],"in":[180],"which":[181],"precharged":[185],"VCCin":[187],"unselected":[189],"sector":[190],"acts":[191],"as":[192],"active":[198],"side":[200],"is":[201],"intentionally":[202],"upsized":[203],"skew":[205],"SA.":[207],"High":[208],"volume":[209],"measurement":[210],"results":[211],"demonstrate":[212],"560":[213],"mV":[214],"Vminat":[215],"400":[216],"MHz/-10":[217],"\u00b0C":[218],"reaches":[220],"2.21":[221],"GHz":[222],"at":[223],"1":[224],"V":[225],"supply.":[226]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}