{"id":"https://openalex.org/W2439909978","doi":"https://doi.org/10.1109/jssc.2016.2557810","title":"A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD","display_name":"A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD","publication_year":2016,"publication_date":"2016-05-30","ids":{"openalex":"https://openalex.org/W2439909978","doi":"https://doi.org/10.1109/jssc.2016.2557810","mag":"2439909978"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2016.2557810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2557810","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088522915","display_name":"Supeng Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Supeng Liu","raw_affiliation_strings":["VIRTUS, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"VIRTUS, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016044907","display_name":"Yuanjin Zheng","orcid":"https://orcid.org/0000-0002-5768-367X"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yuanjin Zheng","raw_affiliation_strings":["VIRTUS, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"VIRTUS, School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5088522915"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.04566459,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"51","issue":"6","first_page":"1361","last_page":"1373"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.993399977684021,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.7444348335266113},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7148798108100891},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.7032699584960938},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.668573260307312},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6443116664886475},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5342788696289062},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49196097254753113},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.46402981877326965},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44284379482269287},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.4374721348285675},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.41788333654403687},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.33929872512817383},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3177032172679901},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2797819972038269},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18470892310142517},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.1438482701778412},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.1024913489818573}],"concepts":[{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.7444348335266113},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7148798108100891},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.7032699584960938},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.668573260307312},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6443116664886475},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5342788696289062},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49196097254753113},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.46402981877326965},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44284379482269287},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.4374721348285675},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.41788333654403687},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.33929872512817383},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3177032172679901},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2797819972038269},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18470892310142517},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.1438482701778412},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.1024913489818573},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2016.2557810","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2016.2557810","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":47,"referenced_works":["https://openalex.org/W1997287970","https://openalex.org/W2017690880","https://openalex.org/W2018588972","https://openalex.org/W2025427953","https://openalex.org/W2028941857","https://openalex.org/W2029477947","https://openalex.org/W2035526941","https://openalex.org/W2036880312","https://openalex.org/W2043250436","https://openalex.org/W2055913428","https://openalex.org/W2058723768","https://openalex.org/W2062952706","https://openalex.org/W2073293474","https://openalex.org/W2077539642","https://openalex.org/W2084208879","https://openalex.org/W2086336002","https://openalex.org/W2096434843","https://openalex.org/W2098011477","https://openalex.org/W2098329558","https://openalex.org/W2108435403","https://openalex.org/W2108458508","https://openalex.org/W2110675623","https://openalex.org/W2120377810","https://openalex.org/W2122847778","https://openalex.org/W2126466849","https://openalex.org/W2127135220","https://openalex.org/W2130227819","https://openalex.org/W2136657726","https://openalex.org/W2139053608","https://openalex.org/W2142610168","https://openalex.org/W2142629786","https://openalex.org/W2149726555","https://openalex.org/W2151340196","https://openalex.org/W2151659230","https://openalex.org/W2151807985","https://openalex.org/W2152144298","https://openalex.org/W2162504624","https://openalex.org/W2164002677","https://openalex.org/W2166155244","https://openalex.org/W2172061240","https://openalex.org/W2177833654","https://openalex.org/W2212877209","https://openalex.org/W2290777953","https://openalex.org/W2548607663","https://openalex.org/W3149129866","https://openalex.org/W6659660600","https://openalex.org/W6680712959"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2043945969","https://openalex.org/W2103754166","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W2223905331","https://openalex.org/W2952154040","https://openalex.org/W2143205859"],"abstract_inverted_index":{"A":[0,39,102],"fractional-N":[1],"digital":[2,81],"phase-locked":[3],"loop":[4],"(DPLL)":[5],"with":[6,129],"ring":[7],"oscillator":[8],"based":[9,45],"injection-locked":[10],"frequency":[11],"divider":[12],"(ILFD)":[13],"and":[14,35,114,144,158,170,176],"parallel":[15,41,60],"sampling":[16,42,54,61,75],"phase":[17,43,165],"samplers":[18],"is":[19,63,68,78,90,120,136,184],"presented.":[20],"The":[21,65,133,152,162,181],"ILFD":[22],"utilizes":[23],"dual":[24],"path":[25],"injection":[26,86],"technique":[27],"to":[28,85,92,97,122],"achieve":[29,123],"wide":[30],"locking":[31],"range":[32],"(4.2-23":[33],"GHz)":[34,127],"low":[36,130],"power":[37,131],"consumption.":[38,132],"low-power":[40],"sampler":[44],"time-to-digital":[46],"converter":[47],"(TDC),":[48],"which":[49,77],"achieves":[50,167],"sub-gate-delay":[51],"resolution":[52,67],"by":[53,70],"the":[55,94,98],"ILFD's":[56],"multi-phase":[57],"outputs":[58],"using":[59],"technique,":[62],"proposed.":[64],"TDC":[66,95],"determined":[69],"delay":[71],"spacing":[72],"between":[73],"successive":[74],"clocks,":[76],"ensured":[79],"through":[80],"calibration":[82,89],"loops.":[83],"Due":[84],"locking,":[87],"no":[88],"required":[91],"normalize":[93],"step":[96],"DCO":[99],"output":[100,157,164],"period.":[101],"hybrid":[103],"high":[104,124],"speed":[105,125],"counter":[106,113],"architecture,":[107],"combining":[108],"a":[109,115,139],"2":[110],"bit":[111,117],"asynchronous":[112],"6":[116],"synchronous":[118],"counter,":[119],"proposed":[121,134],"(>4":[126],"operation":[128],"design":[135],"fabricated":[137],"in":[138],"65":[140],"nm":[141],"CMOS":[142],"process":[143],"occupies":[145],"0.1":[146],"mm":[147],"<sup":[148],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[149],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[150],".":[151],"synthesizer":[153],"covers":[154],"13.6-16.8":[155],"GHz":[156],"dissipates":[159],"8.5":[160],"mW.":[161],"measured":[163,182],"noise":[166],"-89":[168],"dBc/Hz":[169,172],"-125":[171],"at":[173],"100":[174],"kHz":[175],"10":[177],"MHz":[178],"offsets,":[179],"respectively.":[180],"jitter":[183],"less":[185],"than":[186],"0.43":[187],"ps.":[188]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}