{"id":"https://openalex.org/W2286199991","doi":"https://doi.org/10.1109/jssc.2015.2501424","title":"A Compact First-Order Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process","display_name":"A Compact First-Order Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2286199991","doi":"https://doi.org/10.1109/jssc.2015.2501424","mag":"2286199991"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2015.2501424","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2015.2501424","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005935863","display_name":"Takao Oshita","orcid":"https://orcid.org/0000-0001-8060-0118"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Takao Oshita","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038423749","display_name":"Joseph Shor","orcid":"https://orcid.org/0000-0002-9184-8642"},"institutions":[{"id":"https://openalex.org/I4210104622","display_name":"Intel (Israel)","ror":"https://ror.org/027t2s119","country_code":"IL","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210104622"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Joseph Shor","raw_affiliation_strings":["Intel Corporation, Yakum, Israel"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Yakum, Israel","institution_ids":["https://openalex.org/I4210104622"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101664947","display_name":"D. Duarte","orcid":"https://orcid.org/0000-0001-8846-0324"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David E. Duarte","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084666796","display_name":"A. Kornfeld","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Avner Kornfeld","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031530468","display_name":"G. Geannopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"George L. Geannopoulos","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111376807","display_name":"Jonathan Douglas","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Douglas","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034919212","display_name":"Nasser Kurd","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nasser Kurd","raw_affiliation_strings":["Intel Corporation, Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2019,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.76897296,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"51","issue":"2","first_page":"378","last_page":"390"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.592402458190918},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.5868571996688843},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5694921016693115},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4806724488735199},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46626171469688416},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43669313192367554},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37939006090164185},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33128494024276733},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23276951909065247},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.14373892545700073}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.592402458190918},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.5868571996688843},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5694921016693115},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4806724488735199},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46626171469688416},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43669313192367554},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37939006090164185},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33128494024276733},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23276951909065247},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.14373892545700073}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2015.2501424","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2015.2501424","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1486334132","https://openalex.org/W1532201326","https://openalex.org/W1582910515","https://openalex.org/W1969794630","https://openalex.org/W1969965391","https://openalex.org/W1980893811","https://openalex.org/W2012011600","https://openalex.org/W2018657325","https://openalex.org/W2027766075","https://openalex.org/W2030049410","https://openalex.org/W2052895130","https://openalex.org/W2058219874","https://openalex.org/W2065808645","https://openalex.org/W2067900275","https://openalex.org/W2070247293","https://openalex.org/W2070993571","https://openalex.org/W2085177768","https://openalex.org/W2086328585","https://openalex.org/W2104086223","https://openalex.org/W2106071059","https://openalex.org/W2107712601","https://openalex.org/W2112611349","https://openalex.org/W2114410447","https://openalex.org/W2121893773","https://openalex.org/W2145431362","https://openalex.org/W2150423223","https://openalex.org/W2155589054","https://openalex.org/W2157269402","https://openalex.org/W2214300765","https://openalex.org/W6645543914"],"related_works":["https://openalex.org/W2389128124","https://openalex.org/W2364812720","https://openalex.org/W2138725603","https://openalex.org/W1984486060","https://openalex.org/W2050335563","https://openalex.org/W3001913892","https://openalex.org/W98453623","https://openalex.org/W2340624421","https://openalex.org/W2109445684","https://openalex.org/W2081082331"],"abstract_inverted_index":{"On":[0],"complex":[1],"system-on-chips":[2],"(SOCs),":[3],"a":[4,36,55,75,118],"compact":[5,37,57,130],"on-die":[6,28,42],"analog-to-digital":[7],"converter":[8],"(ADC)":[9],"is":[10,52],"required":[11],"in":[12,15,45,126],"high-volume":[13],"testing,":[14],"order":[16],"to":[17,53,66,101],"reduce":[18],"the":[19,24,68,88,103,129],"test":[20,25],"time":[21],"and":[22,106],"improve":[23],"coverage":[26],"of":[27,70,120,123,128,132],"analog":[29,72],"intellectual":[30],"properties":[31],"(IPs).":[32],"This":[33],"paper":[34],"presents":[35],"first-order":[38],"\u03a3\u0394":[39],"modulator":[40,81,116],"for":[41,111],"voltage":[43],"measurements":[44],"such":[46],"applications.":[47],"The":[48,79,115],"primary":[49],"design":[50],"focus":[51],"achieve":[54],"highly":[56],"area":[58,90,131],"so":[59],"that":[60],"many":[61],"instances":[62],"can":[63],"be":[64],"integrated":[65],"cover":[67],"testing":[69],"multiple":[71],"IPs":[73],"on":[74],"single":[76],"chip":[77],"die.":[78],"proposed":[80],"deploys":[82],"an":[83],"inverter-based":[84],"architecture":[85],"which":[86],"enables":[87],"aggressive":[89],"reduction.":[91],"There":[92],"are":[93],"two":[94],"new":[95],"additional":[96],"enhancements:":[97],"1)":[98],"hardware":[99],"dithering":[100],"minimize":[102],"limit-cycling":[104],"effect":[105],"2)":[107],"time-multiplexed":[108],"pseudodifferential":[109],"operation":[110],"common":[112],"mode":[113],"rejection.":[114],"exhibits":[117],"figure":[119],"merit":[121],"(FOM)":[122],"554.7":[124],"fJ/conv-step,":[125],"spite":[127],"only":[133],"0.00023":[134],"mm2.":[135]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":6}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2016-06-24T00:00:00"}
