{"id":"https://openalex.org/W1592084739","doi":"https://doi.org/10.1109/jssc.2015.2433269","title":"Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies","display_name":"Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies","publication_year":2015,"publication_date":"2015-06-04","ids":{"openalex":"https://openalex.org/W1592084739","doi":"https://doi.org/10.1109/jssc.2015.2433269","mag":"1592084739"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2015.2433269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2015.2433269","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029840448","display_name":"Jri Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jri Lee","raw_affiliation_strings":["Atilia Technology, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Atilia Technology, Taipei, Taiwan","institution_ids":[]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103125796","display_name":"Ping-Chuan Chiang","orcid":"https://orcid.org/0000-0002-2004-9413"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ping-Chuan Chiang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017157916","display_name":"Pen-Jui Peng","orcid":"https://orcid.org/0000-0001-5736-5746"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Pen-Jui Peng","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065743488","display_name":"Li\u2010Yang Chen","orcid":"https://orcid.org/0000-0002-5890-4227"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Li-Yang Chen","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082592580","display_name":"Chih-Chi Weng","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Chi Weng","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5029840448"],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":8.5995,"has_fulltext":false,"cited_by_count":149,"citation_normalized_percentile":{"value":0.98001606,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":"50","issue":"9","first_page":"2061","last_page":"2073"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.9615966081619263},{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.8500913977622986},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.7467725276947021},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.7170261740684509},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6722375750541687},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5908117294311523},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5891585350036621},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5255735516548157},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32039111852645874},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2906789481639862},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.2807064652442932},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1349392533302307},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.06308755278587341}],"concepts":[{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.9615966081619263},{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.8500913977622986},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.7467725276947021},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.7170261740684509},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6722375750541687},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5908117294311523},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5891585350036621},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5255735516548157},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32039111852645874},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2906789481639862},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.2807064652442932},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1349392533302307},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.06308755278587341},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2015.2433269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2015.2433269","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6399999856948853}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323092","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70"},{"id":"https://openalex.org/F4320323900","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1511784851","https://openalex.org/W1985419217","https://openalex.org/W1993254104","https://openalex.org/W2029291108","https://openalex.org/W2069451201","https://openalex.org/W2101048469","https://openalex.org/W2101132714","https://openalex.org/W2102506502","https://openalex.org/W2110286059","https://openalex.org/W2122977511","https://openalex.org/W2128347794","https://openalex.org/W2129305974","https://openalex.org/W2132897890","https://openalex.org/W2139408424","https://openalex.org/W2142626251","https://openalex.org/W2150983492","https://openalex.org/W2156103315","https://openalex.org/W2167891824","https://openalex.org/W3149714014","https://openalex.org/W4246911246","https://openalex.org/W6646499804","https://openalex.org/W6657737696","https://openalex.org/W6675426285","https://openalex.org/W6682300465"],"related_works":["https://openalex.org/W2130047965","https://openalex.org/W3145088891","https://openalex.org/W2392047957","https://openalex.org/W3087888791","https://openalex.org/W2957422867","https://openalex.org/W2143950660","https://openalex.org/W2060627912","https://openalex.org/W2382232495","https://openalex.org/W2734818042","https://openalex.org/W3160420002"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"two":[3],"ultra-high-speed":[4],"SerDes":[5],"dedicated":[6],"for":[7,94],"PAM4":[8,13,34],"and":[9,22,32,42,48,61],"NRZ":[10,52,64],"data.":[11,51,79],"The":[12],"TX":[14,53],"incorporates":[15],"an":[16],"output":[17],"driver":[18],"with":[19,58,69,87],"3-tap":[20],"FFE":[21],"adjustable":[23],"weighting":[24],"to":[25,46,73],"deliver":[26],"clean":[27],"outputs":[28],"at":[29],"4":[30],"levels,":[31],"the":[33,50,75],"RX":[35,65],"employs":[36],"a":[37,55],"purely":[38],"linear":[39,67],"full-rate":[40],"CDR":[41],"CTLE/1-tap":[43],"DFE":[44],"combination":[45],"recover":[47],"demultiplex":[49],"includes":[54],"tree-structure":[56],"MUX":[57],"built-in":[59],"PLL":[60],"phase":[62],"aligner.":[63],"adopts":[66],"PD":[68],"special":[70],"vernier":[71],"technique":[72],"handle":[74],"56":[76],"Gb/s":[77],"input":[78],"All":[80],"chips":[81],"have":[82],"been":[83],"verified":[84],"in":[85],"silicon":[86],"reasonable":[88],"performance,":[89],"providing":[90],"prospective":[91],"design":[92],"examples":[93],"next-generation":[95],"400":[96],"GbE.":[97]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":16},{"year":2024,"cited_by_count":15},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":17},{"year":2021,"cited_by_count":12},{"year":2020,"cited_by_count":15},{"year":2019,"cited_by_count":18},{"year":2018,"cited_by_count":19},{"year":2017,"cited_by_count":17},{"year":2016,"cited_by_count":7}],"updated_date":"2026-03-05T09:29:38.588285","created_date":"2025-10-10T00:00:00"}