{"id":"https://openalex.org/W2022035810","doi":"https://doi.org/10.1109/jssc.2014.2369508","title":"A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 \u00d7 16 Network-on-Chip in 22 nm Tri-Gate CMOS","display_name":"A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 \u00d7 16 Network-on-Chip in 22 nm Tri-Gate CMOS","publication_year":2014,"publication_date":"2014-12-11","ids":{"openalex":"https://openalex.org/W2022035810","doi":"https://doi.org/10.1109/jssc.2014.2369508","mag":"2022035810"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2014.2369508","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2014.2369508","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090166397","display_name":"Gregory Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory Chen","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark A. Anders","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081032347","display_name":"Himanshu Kaul","orcid":"https://orcid.org/0000-0003-1586-7486"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075692568","display_name":"Sudhir Satpathy","orcid":"https://orcid.org/0000-0003-3511-3526"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhir K. Satpathy","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu K. Mathew","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109275074","display_name":"Steven K. Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven K. Hsu","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram K. Krishnamurthy","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shekhar Borkar","raw_affiliation_strings":["Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","[Intel, Hillsboro, OR, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Circuit Research Lab, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Intel, Hillsboro, OR, USA]","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":11.5165,"has_fulltext":false,"cited_by_count":55,"citation_normalized_percentile":{"value":0.98631625,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"50","issue":"1","first_page":"59","last_page":"67"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5216619968414307},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.45685508847236633},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.42769408226013184},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.4196714162826538},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3589133024215698},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34693098068237305},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33171015977859497},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17088329792022705},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16468575596809387}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5216619968414307},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.45685508847236633},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.42769408226013184},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.4196714162826538},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3589133024215698},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34693098068237305},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33171015977859497},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17088329792022705},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16468575596809387}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2014.2369508","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2014.2369508","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1991991600","https://openalex.org/W2004984689","https://openalex.org/W2017503457","https://openalex.org/W2035699920","https://openalex.org/W2037181413","https://openalex.org/W2047642791","https://openalex.org/W2058066847","https://openalex.org/W2072607061","https://openalex.org/W2077505860","https://openalex.org/W2115611348","https://openalex.org/W2120538858","https://openalex.org/W2147657871","https://openalex.org/W2159243841","https://openalex.org/W6654834059","https://openalex.org/W6662364431","https://openalex.org/W6668441287"],"related_works":["https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2603824091","https://openalex.org/W2439487276","https://openalex.org/W2560886726","https://openalex.org/W2472457643","https://openalex.org/W2510977931","https://openalex.org/W2091258882","https://openalex.org/W2541438272","https://openalex.org/W3006485811"],"abstract_inverted_index":{"A":[0],"16":[1,3],"\u00d7":[2],"mesh":[4],"network-on-chip":[5],"(NoC)":[6],"is":[7],"fabricated":[8],"in":[9,19,32,107,116,138],"22":[10],"nm":[11],"tri-gate":[12],"CMOS":[13],"for":[14,103,130,156],"high-throughput,":[15],"energy-efficient":[16],"on-chip":[17],"interconnect":[18],"multi-core":[20],"processors":[21],"and":[22,36,42,56,61,75,83,113,135],"systems-on-chip.":[23],"The":[24,87],"NoC":[25,88],"connects":[26],"256":[27],"nodes":[28],"that":[29],"are":[30],"each":[31],"their":[33],"own":[34],"voltage":[35],"clock":[37,53],"domain":[38],"using":[39],"5-port":[40],"routers":[41],"112":[43],"b,":[44],"855":[45],"\u03bcm":[46],"data":[47,73,85],"links.":[48],"Source-synchronous":[49],"operation":[50,102,158,166],"eliminates":[51],"global":[52],"distribution":[54],"power":[55,175],"adapts":[57],"to":[58,110,123,141,145,168,177],"process,":[59],"voltage,":[60],"temperature":[62],"variations.":[63],"Hybrid":[64],"packet/circuit":[65,128],"switching":[66,129],"improves":[67],"energy":[68,139,151],"efficiency":[69,140,152],"by":[70],"removing":[71],"intra-route":[72],"storage":[74],"increases":[76],"throughput":[77,94],"with":[78,173],"parallel":[79],"packet-switched":[80],"channel":[81],"setup":[82],"circuit-switched":[84,117],"transfer.":[86],"achieves:":[89],"i)":[90],"20.2":[91],"Tb/s":[92,112],"total":[93],"at":[95,119,159],"0.9":[96],"V,":[97],"25":[98,162,171],"\u00b0C;":[99,163],"ii)":[100],"source-synchronous":[101],"a":[104,131,149],"2.7\u00d7":[105],"increase":[106,137],"bisection":[108],"bandwidth":[109],"2.8":[111],"93%":[114],"reduction":[115],"latency":[118,133],"407":[120],"ps/hop,":[121],"compared":[122,144],"synchronous":[124],"design;":[125],"iii)":[126],"hybrid":[127],"62%":[132],"improvement":[134],"55%":[136],"7.0":[142],"Tb/s/W,":[143],"packet":[146],"switching;":[147],"iv)":[148],"peak":[150],"of":[153],"18.3":[154],"Tb/s/W":[155],"near-threshold":[157],"430":[160],"mV,":[161,170],"v)":[164],"ultra-low-voltage":[165],"down":[167],"340":[169],"\u00b0C,":[172],"router":[174],"scaling":[176],"363":[178],"\u03bcW.":[179]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":11},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":10},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
