{"id":"https://openalex.org/W2032859412","doi":"https://doi.org/10.1109/jssc.2013.2296529","title":"A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator","display_name":"A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator","publication_year":2014,"publication_date":"2014-01-30","ids":{"openalex":"https://openalex.org/W2032859412","doi":"https://doi.org/10.1109/jssc.2013.2296529","mag":"2032859412"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2013.2296529","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2296529","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111705984","display_name":"Jingxue Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jingxue Lu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033170080","display_name":"Hye-Jeong Song","orcid":"https://orcid.org/0009-0003-8505-9561"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyejeong Song","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025262826","display_name":"Ranjit Gharpurey","orcid":"https://orcid.org/0000-0002-3446-1564"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ranjit Gharpurey","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Dept. of Electr. &, Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111705984"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":1.256,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.82348541,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"49","issue":"3","first_page":"729","last_page":"739"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7384215593338013},{"id":"https://openalex.org/keywords/pulse-width-modulation","display_name":"Pulse-width modulation","score":0.7019342184066772},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5854853987693787},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.5847408771514893},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5803353190422058},{"id":"https://openalex.org/keywords/total-harmonic-distortion","display_name":"Total harmonic distortion","score":0.5372189879417419},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4711250960826874},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4702405333518982},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4572529196739197},{"id":"https://openalex.org/keywords/pulse-generator","display_name":"Pulse generator","score":0.4398874044418335},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4362514317035675},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43513041734695435},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.36337172985076904},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2857617139816284}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7384215593338013},{"id":"https://openalex.org/C92746544","wikidata":"https://www.wikidata.org/wiki/Q585184","display_name":"Pulse-width modulation","level":3,"score":0.7019342184066772},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5854853987693787},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.5847408771514893},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5803353190422058},{"id":"https://openalex.org/C42156128","wikidata":"https://www.wikidata.org/wiki/Q162641","display_name":"Total harmonic distortion","level":3,"score":0.5372189879417419},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4711250960826874},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4702405333518982},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4572529196739197},{"id":"https://openalex.org/C51319974","wikidata":"https://www.wikidata.org/wiki/Q3509564","display_name":"Pulse generator","level":3,"score":0.4398874044418335},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4362514317035675},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43513041734695435},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.36337172985076904},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2857617139816284}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2013.2296529","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2296529","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1495955379","https://openalex.org/W1965142699","https://openalex.org/W2030066358","https://openalex.org/W2044596837","https://openalex.org/W2057810279","https://openalex.org/W2058941468","https://openalex.org/W2098427444","https://openalex.org/W2099944833","https://openalex.org/W2104527935","https://openalex.org/W2143469102","https://openalex.org/W2146422534","https://openalex.org/W2164002677","https://openalex.org/W2170119490","https://openalex.org/W2170147187"],"related_works":["https://openalex.org/W2034349229","https://openalex.org/W4366783034","https://openalex.org/W1972415042","https://openalex.org/W2474043983","https://openalex.org/W2078513307","https://openalex.org/W2566880546","https://openalex.org/W2544336511","https://openalex.org/W2144737022","https://openalex.org/W2000633969","https://openalex.org/W1978186604"],"abstract_inverted_index":{"A":[0],"Class-D":[1],"line":[2],"driver":[3],"that":[4,74,104],"utilizes":[5],"a":[6,37,49,54,65,70,84,90,94,101,125],"phase-locked":[7],"loop":[8,24],"(PLL)":[9],"for":[10,64,89,117,124],"PWM":[11,79],"generation":[12],"is":[13,34,115,134],"presented.":[14],"The":[15,42,59,112,131],"principle":[16],"of":[17,86,96,128],"operation":[18],"and":[19,27,69],"implementation":[20,33],"details":[21],"relating":[22],"to":[23],"stability,":[25],"linearity":[26],"noise":[28],"performance":[29],"are":[30,75],"analyzed.":[31],"An":[32],"presented":[35],"in":[36,78],"130":[38],"nm":[39],"CMOS":[40],"process.":[41],"amplifier":[43],"can":[44,82,105],"deliver":[45],"1.2":[46],"W":[47,123],"into":[48],"6.8":[50],"\u03a9":[51],"load":[52],"with":[53,93],"4.8":[55],"V":[56],"power":[57,119],"supply.":[58],"architecture":[60],"eliminates":[61],"the":[62],"requirements":[63],"high-quality":[66],"carrier":[67],"generator":[68],"high-speed":[71],"voltage":[72],"comparator":[73],"often":[76],"required":[77],"implementations.":[80],"It":[81],"achieve":[83],"THD":[85],"-65":[87],"dB,":[88],"sinusoidal":[91],"input":[92],"frequency":[95,103,127],"60":[97],"kHz,":[98],"while":[99],"employing":[100],"switching":[102,126],"be":[106],"as":[107,109],"high":[108],"20":[110],"MHz.":[111,130],"peak":[113],"efficiency":[114],"83%":[116],"output":[118],"larger":[120],"than":[121],"1":[122],"10":[129],"die":[132],"area":[133],"2.25":[135],"mm":[136],"<sup":[137],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[138],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[139],".":[140]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}