{"id":"https://openalex.org/W2094060435","doi":"https://doi.org/10.1109/jssc.2013.2279052","title":"A Scalable 0.128\u20131 Tb/s, 0.8\u20132.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS","display_name":"A Scalable 0.128\u20131 Tb/s, 0.8\u20132.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS","publication_year":2013,"publication_date":"2013-09-06","ids":{"openalex":"https://openalex.org/W2094060435","doi":"https://doi.org/10.1109/jssc.2013.2279052","mag":"2094060435"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2013.2279052","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2279052","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053540874","display_name":"Mozhgan Mansuri","orcid":"https://orcid.org/0000-0002-0277-7775"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mozhgan Mansuri","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090419770","display_name":"James Jaussi","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James E. Jaussi","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035029367","display_name":"Joseph Kennedy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joseph T. Kennedy","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062381369","display_name":"Tzu-Chien Hsueh","orcid":"https://orcid.org/0000-0002-8596-6976"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tzu-Chien Hsueh","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048584348","display_name":"Sudip Shekhar","orcid":"https://orcid.org/0000-0003-0383-1929"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudip Shekhar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023328166","display_name":"Ganesh Balamurugan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ganesh Balamurugan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010946517","display_name":"Frank O\u2019Mahony","orcid":"https://orcid.org/0000-0001-7961-9452"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Frank O'Mahony","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010693797","display_name":"Clark Roberts","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Clark Roberts","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049783709","display_name":"Randy Mooney","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Randy Mooney","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089280659","display_name":"Bryan Casper","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bryan Casper","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":3.0533,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.92111574,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"48","issue":"12","first_page":"3229","last_page":"3242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7389622330665588},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5123640298843384},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5106244683265686},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.4873822331428528},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.453889399766922},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4422066807746887},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.4404643177986145},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4219897985458374},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4153823256492615},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.378919780254364},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.261646032333374},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25865304470062256},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25113749504089355},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.18081626296043396}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7389622330665588},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5123640298843384},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5106244683265686},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.4873822331428528},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.453889399766922},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4422066807746887},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.4404643177986145},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4219897985458374},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4153823256492615},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.378919780254364},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.261646032333374},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25865304470062256},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25113749504089355},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18081626296043396}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2013.2279052","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2279052","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1986315961","https://openalex.org/W2062327827","https://openalex.org/W2103745509","https://openalex.org/W2115278151","https://openalex.org/W2119440008","https://openalex.org/W2135196523","https://openalex.org/W2137800538","https://openalex.org/W2139132358","https://openalex.org/W2145598637","https://openalex.org/W2157486149","https://openalex.org/W2160740950","https://openalex.org/W2162364499","https://openalex.org/W2164188348","https://openalex.org/W2170215783","https://openalex.org/W2176473673","https://openalex.org/W2188104546","https://openalex.org/W2789212828","https://openalex.org/W3144013075","https://openalex.org/W3149917762","https://openalex.org/W6686944249"],"related_works":["https://openalex.org/W2145876553","https://openalex.org/W2139221936","https://openalex.org/W2017861587","https://openalex.org/W2019727651","https://openalex.org/W2790811635","https://openalex.org/W2362169398","https://openalex.org/W2139353707","https://openalex.org/W3083915265","https://openalex.org/W1982003134","https://openalex.org/W2033219015"],"abstract_inverted_index":{"A":[0,105,177],"scalable":[1,134],"64-lane":[2],"chip-to-chip":[3],"I/O,":[4],"with":[5,96],"per-lane":[6,49,81],"data":[7,50,82],"rate":[8,51,83],"of":[9,23,63,84,93,150,155],"2-16":[10],"Gb/s":[11,54],"is":[12],"demonstrated":[13],"in":[14],"32-nm":[15],"low-power":[16],"CMOS":[17,129],"technology.":[18],"At":[19],"maximum":[20,65,80],"aggregate":[21,94],"bandwidth":[22,44,66,95],"1.024":[24,91],"Tb/s":[25,92],"across":[26,115,161],"50-cm":[27],"channel":[28,186],"length,":[29],"the":[30,48,64,75,146,162],"link":[31,76,173],"consumes":[32],"2.7":[33],"W":[34],"from":[35,101],"a":[36,72,79,102,132],"1.08-V":[37],"supply,":[38],"corresponding":[39],"to":[40,52,58,90,112,118,184],"2.6":[41],"pJ/bit.":[42],"As":[43],"demand":[45],"decreases,":[46],"scaling":[47],"4":[53],"and":[55,121,128,157,175],"power":[56,99],"supply":[57,142],"0.65":[59],"V":[60],"provides":[61,165,181],"1/4":[62],"while":[67],"consuming":[68],"0.2":[69],"W.":[70],"Across":[71],"1-m":[73],"channel,":[74],"operates":[77],"at":[78,145],"16":[85],"Gb/s;":[86],"thus,":[87,171],"providing":[88],"up":[89],"3.2":[97],"pJ/bit":[98],"efficiency":[100],"1.15-V":[103],"supply.":[104],"length-matched":[106],"dense":[107],"interconnect":[108],"topology":[109],"allows":[110],"clocking":[111,130],"be":[113],"shared":[114],"multiple":[116],"lanes":[117],"reduce":[119],"area":[120],"power.":[122,176],"Reconfigurable":[123],"current/voltage":[124],"mode":[125],"transmitter":[126],"driver":[127],"enable":[131],"highly":[133],"power-efficient":[135],"link.":[136],"Optional":[137],"low-dropout":[138],"regulators":[139],"provide":[140],">22-dB":[141],"noise":[143],"rejection":[144],"package":[147],"resonance":[148],"frequency":[149],"200":[151],"MHz.":[152],"System-level":[153],"optimization":[154],"duty-cycle":[156],"quadrature":[158],"error":[159],"correctors":[160],"clock":[163,167],"hierarchy":[164],"optimized":[166],"phase":[168],"placement":[169],"and,":[170],"enhances":[172],"performance":[174],"lane":[178],"failover":[179],"mechanism":[180],"design":[182],"robustness":[183],"mitigate":[185],"or":[187],"circuit":[188],"defects.":[189],"The":[190],"active":[191],"circuitry":[192],"occupies":[193],"1.3":[194],"mm":[195],"<sup":[196],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[197],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[198],".":[199]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
