{"id":"https://openalex.org/W2102397476","doi":"https://doi.org/10.1109/jssc.2013.2259038","title":"SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation","display_name":"SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation","publication_year":2013,"publication_date":"2013-07-19","ids":{"openalex":"https://openalex.org/W2102397476","doi":"https://doi.org/10.1109/jssc.2013.2259038","mag":"2102397476"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2013.2259038","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2259038","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/6564404/06515159.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/4/6564404/06515159.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049087262","display_name":"Eustace Painkras","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Eustace Painkras","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015816826","display_name":"Luis A. Plana","orcid":"https://orcid.org/0000-0002-6113-3929"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Luis A. Plana","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053098822","display_name":"Jim Garside","orcid":"https://orcid.org/0000-0001-8812-4742"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jim Garside","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047132316","display_name":"Steve Temple","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Steve Temple","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015180981","display_name":"Francesco Galluppi","orcid":"https://orcid.org/0000-0001-8552-2999"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Francesco Galluppi","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109675287","display_name":"Cameron Patterson","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Cameron Patterson","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039574409","display_name":"David Lester","orcid":"https://orcid.org/0000-0002-7267-291X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David R. Lester","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060418055","display_name":"A.D. Brown","orcid":"https://orcid.org/0000-0002-0700-9433"},"institutions":[{"id":"https://openalex.org/I43439940","display_name":"University of Southampton","ror":"https://ror.org/01ryk1543","country_code":"GB","type":"education","lineage":["https://openalex.org/I43439940"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Andrew D. Brown","raw_affiliation_strings":["Electronics and Electrical Engineering, University of Southampton, Southampton, UK","Electron. & Electr. Eng., Univ. of Southampton, Southampton, UK"],"affiliations":[{"raw_affiliation_string":"Electronics and Electrical Engineering, University of Southampton, Southampton, UK","institution_ids":["https://openalex.org/I43439940"]},{"raw_affiliation_string":"Electron. & Electr. Eng., Univ. of Southampton, Southampton, UK","institution_ids":["https://openalex.org/I43439940"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083177159","display_name":"Steve Furber","orcid":"https://orcid.org/0000-0002-6524-3367"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Steve B. Furber","raw_affiliation_strings":["Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#"],"affiliations":[{"raw_affiliation_string":"Advanced Processor Technologies Group, School of Computer Science, University of Manchester, Manchester, UK","institution_ids":["https://openalex.org/I28407311"]},{"raw_affiliation_string":"Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK#TAB#","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5049087262"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":15.4199,"has_fulltext":true,"cited_by_count":504,"citation_normalized_percentile":{"value":0.99313881,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":"48","issue":"8","first_page":"1943","last_page":"1953"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8413326740264893},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7543555498123169},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.6075490117073059},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5704537630081177},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5633476972579956},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5403050184249878},{"id":"https://openalex.org/keywords/spiking-neural-network","display_name":"Spiking neural network","score":0.5352545380592346},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5259376168251038},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.46170005202293396},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4105584919452667},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3891250193119049},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.32838618755340576},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2655959725379944},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.19090145826339722},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11926347017288208}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8413326740264893},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7543555498123169},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.6075490117073059},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5704537630081177},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5633476972579956},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5403050184249878},{"id":"https://openalex.org/C11731999","wikidata":"https://www.wikidata.org/wiki/Q9067355","display_name":"Spiking neural network","level":3,"score":0.5352545380592346},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5259376168251038},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.46170005202293396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4105584919452667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3891250193119049},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.32838618755340576},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2655959725379944},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.19090145826339722},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11926347017288208},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/jssc.2013.2259038","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2259038","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/6564404/06515159.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},{"id":"pmh:oai:pure.atira.dk:openaire/f4406b35-9f30-4f93-9ad3-f03bf572dbe0","is_oa":true,"landing_page_url":"https://research.manchester.ac.uk/en/publications/f4406b35-9f30-4f93-9ad3-f03bf572dbe0","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Painkras, E, Plana, L A, Garside, J, Temple, S, Galluppi, F, Patterson, C, Lester, D R, Brown, A D & Furber, S B 2013, 'SpiNNaker: A 1-W 18-core system-on-chip for massively-parallel neural network simulation', IEEE Journal of Solid State Circuits, vol. 48, no. 8, 6515159, pp. 1943-1953. https://doi.org/10.1109/JSSC.2013.2259038","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:eprints.soton.ac.uk:350493","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306401019","display_name":"ePrints Soton (University of Southampton)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I43439940","host_organization_name":"University of Southampton","host_organization_lineage":["https://openalex.org/I43439940"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Article"},{"id":"pmh:oai:pure.atira.dk:publications/f4406b35-9f30-4f93-9ad3-f03bf572dbe0","is_oa":true,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/spinnaker-a-1w-18core-systemonchip-for-massivelyparallel-neural-network-simulation(f4406b35-9f30-4f93-9ad3-f03bf572dbe0).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Painkras, E, Plana, L A, Garside, J, Temple, S, Galluppi, F, Patterson, C, Lester, D R, Brown, A D & Furber, S B 2013, 'SpiNNaker: A 1-W 18-core system-on-chip for massively-parallel neural network simulation', IEEE Journal of Solid State Circuits, vol. 48, no. 8, 6515159, pp. 1943-1953. https://doi.org/10.1109/JSSC.2013.2259038","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:uobrep.openrepository.com:10547/593703","is_oa":false,"landing_page_url":"http://hdl.handle.net/10547/593703","pdf_url":null,"source":{"id":"https://openalex.org/S4306400178","display_name":"University of Bedfordshire Repository (University of Bedfordshire)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I147554453","host_organization_name":"University of Bedfordshire","host_organization_lineage":["https://openalex.org/I147554453"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":{"id":"doi:10.1109/jssc.2013.2259038","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2259038","pdf_url":"https://ieeexplore.ieee.org/ielx7/4/6564404/06515159.pdf","source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.5799999833106995,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G1934935867","display_name":null,"funder_award_id":"Engineering and Physical Sciences R","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2811095472","display_name":"Biologically-Inspired Massively Parallel Architectures - computing beyond a million processors","funder_award_id":"EP/G015740/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G2876104676","display_name":"A scalable chip multiprocessor for large-scale neural simulation","funder_award_id":"EP/D07908X/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G323116497","display_name":null,"funder_award_id":"EP/G015740/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7996027513","display_name":null,"funder_award_id":"EP/D079594/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8450547870","display_name":null,"funder_award_id":"EP/G015775/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2102397476.pdf","grobid_xml":"https://content.openalex.org/works/W2102397476.grobid-xml"},"referenced_works_count":34,"referenced_works":["https://openalex.org/W1511118701","https://openalex.org/W1512746852","https://openalex.org/W1568532871","https://openalex.org/W1583248465","https://openalex.org/W1925797971","https://openalex.org/W1964659356","https://openalex.org/W1972827198","https://openalex.org/W1985940938","https://openalex.org/W1997078229","https://openalex.org/W2007983873","https://openalex.org/W2010146840","https://openalex.org/W2031273683","https://openalex.org/W2058443342","https://openalex.org/W2069552454","https://openalex.org/W2087058693","https://openalex.org/W2092003138","https://openalex.org/W2100998211","https://openalex.org/W2112327737","https://openalex.org/W2112683930","https://openalex.org/W2114052846","https://openalex.org/W2114691690","https://openalex.org/W2124266443","https://openalex.org/W2136278394","https://openalex.org/W2153041354","https://openalex.org/W2156640153","https://openalex.org/W2156903694","https://openalex.org/W2161080065","https://openalex.org/W2161311656","https://openalex.org/W2164653071","https://openalex.org/W2171471042","https://openalex.org/W2338037132","https://openalex.org/W6630531298","https://openalex.org/W6640161409","https://openalex.org/W6682459074"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W2155261584","https://openalex.org/W2584231425","https://openalex.org/W2042919702","https://openalex.org/W2150611273","https://openalex.org/W1970433854","https://openalex.org/W4207086172","https://openalex.org/W2023867642","https://openalex.org/W4225981436","https://openalex.org/W2731059981"],"abstract_inverted_index":{"The":[0,59],"modelling":[1],"of":[2,5,14,139,148,160],"large":[3],"systems":[4],"spiking":[6],"neurons":[7,50],"is":[8,26,63,70],"computationally":[9],"very":[10,106],"demanding":[11,107],"in":[12,55,85,128],"terms":[13],"processing":[15],"power":[16,146,171],"and":[17,37,51,113,142,168,172],"communication.":[18],"SpiNNaker":[19,65,111,121,163],"-":[20,25],"Spiking":[21],"Neural":[22],"Network":[23],"architecture":[24],"a":[27,35,48,52,71,90,129,136,144],"massively":[28],"parallel":[29],"computer":[30],"system":[31,78],"designed":[32],"to":[33,47],"provide":[34],"cost-effective":[36],"flexible":[38],"simulator":[39],"for":[40,104],"neuroscience":[41],"experiments.":[42],"It":[43],"can":[44],"model":[45],"up":[46],"billion":[49],"trillion":[53],"synapses":[54],"biological":[56],"real":[57],"time.":[58],"basic":[60],"building":[61],"block":[62],"the":[64,101,110,120,157],"Chip":[66],"Multiprocessor":[67],"(CMP),":[68],"which":[69,123],"custom-designed":[72],"globally":[73],"asynchronous":[74,93],"locally":[75],"synchronous":[76,86],"(GALS)":[77],"with":[79],"18":[80],"ARM968":[81],"processor":[82,153],"nodes":[83],"residing":[84],"islands,":[87],"surrounded":[88],"by":[89],"lightweight,":[91],"packet-switched":[92],"communications":[94],"infrastructure.":[95],"In":[96],"this":[97],"paper,":[98],"we":[99],"review":[100],"design":[102],"requirements":[103],"its":[105,114],"target":[108],"application,":[109],"micro-architecture":[112],"implementation":[115],"issues.":[116],"We":[117],"also":[118],"evaluate":[119],"CMP,":[122],"contains":[124],"100":[125],"million":[126],"transistors":[127],"102-mm":[130],"<sup":[131],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[132],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[133],"die,":[134],"provides":[135],"peak":[137,145],"performance":[138,173],"3.96":[140],"GIPS,":[141],"has":[143],"consumption":[147],"1":[149],"W":[150],"when":[151],"all":[152],"cores":[154],"operate":[155],"at":[156],"nominal":[158],"frequency":[159],"180":[161],"MHz.":[162],"chips":[164],"are":[165],"fully":[166],"operational":[167],"meet":[169],"their":[170],"requirements.":[174]},"counts_by_year":[{"year":2026,"cited_by_count":6},{"year":2025,"cited_by_count":58},{"year":2024,"cited_by_count":62},{"year":2023,"cited_by_count":80},{"year":2022,"cited_by_count":56},{"year":2021,"cited_by_count":46},{"year":2020,"cited_by_count":33},{"year":2019,"cited_by_count":32},{"year":2018,"cited_by_count":42},{"year":2017,"cited_by_count":25},{"year":2016,"cited_by_count":26},{"year":2015,"cited_by_count":23},{"year":2014,"cited_by_count":12},{"year":2013,"cited_by_count":3}],"updated_date":"2026-04-04T08:04:53.788161","created_date":"2025-10-10T00:00:00"}