{"id":"https://openalex.org/W2075096358","doi":"https://doi.org/10.1109/jssc.2013.2258815","title":"An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel\u00ae Xeon\u00ae Processor E5 Family","display_name":"An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel\u00ae Xeon\u00ae Processor E5 Family","publication_year":2013,"publication_date":"2013-07-19","ids":{"openalex":"https://openalex.org/W2075096358","doi":"https://doi.org/10.1109/jssc.2013.2258815","mag":"2075096358"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2013.2258815","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2258815","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007392914","display_name":"Min Huang","orcid":"https://orcid.org/0000-0003-3793-968X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Min Huang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062339862","display_name":"Moty Mehalel","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Moty Mehalel","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028152387","display_name":"Ramesh Arvapalli","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ramesh Arvapalli","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100930532","display_name":"Songnian He","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Songnian He","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corp., Santa Clara, CA, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Santa Clara, CA, , USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.2002,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.82009192,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"48","issue":"8","first_page":"1954","last_page":"1962"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6545426845550537},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5581616759300232},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.5006883144378662},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3793606758117676}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6545426845550537},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5581616759300232},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.5006883144378662},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3793606758117676}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2013.2258815","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2258815","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337392","display_name":"Division of Electrical, Communications and Cyber Systems","ror":"https://ror.org/01krpsy48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1996086722","https://openalex.org/W2030049410","https://openalex.org/W2044443802","https://openalex.org/W6638791736"],"related_works":["https://openalex.org/W2357388125","https://openalex.org/W2981664121","https://openalex.org/W2936534257","https://openalex.org/W2887282140","https://openalex.org/W2526069705","https://openalex.org/W2741421049","https://openalex.org/W2108305411","https://openalex.org/W1980140364","https://openalex.org/W2024016913","https://openalex.org/W2295585735"],"abstract_inverted_index":{"An":[0],"energy":[1,105,128],"efficient":[2,106],"on-die":[3],"20-way":[4],"set":[5],"associative":[6],"L3":[7,48,95,122],"cache":[8,49,96,123],"of":[9,37],"size":[10],"20":[11],"MB":[12],"for":[13,58,71],"the":[14,32,59,72],"Intel":[15],"<sup":[16,20,54,67],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[17,21,55,68],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00ae</sup>":[18,22],"Xeon":[19],"processor":[23],"E5":[24],"family":[25],"is":[26,29],"presented.":[27],"It":[28],"manufactured":[30],"in":[31],"Intel's":[33],"32-nm":[34],"second":[35],"generation":[36],"high-K":[38],"dielectric":[39],"metal":[40,45],"gate":[41],"process":[42],"with":[43],"9-copper":[44],"layers.":[46],"The":[47,77,93,108,121],"design":[50,91,113],"uses":[51],"0.2119":[52],"um":[53,66],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[56,69],"cell":[57,70],"high":[60,73,101],"density":[61,102],"big":[62],"array":[63],"and":[64,88,104,110,117,135],"0.2725":[65],"performance":[74],"smaller":[75],"arrays.":[76],"power":[78,85],"efficiency":[79,129],"was":[80],"achieved":[81],"by":[82],"employing":[83],"advanced":[84],"saving":[86],"schemes":[87],"effective":[89,109],"Vccmin":[90],"techniques.":[92],"proposed":[94],"topology":[97],"seamlessly":[98],"supports":[99],"a":[100],"modular":[103],"designs.":[107],"rich":[111],"redundancy":[112],"improves":[114],"both":[115],"yield":[116],"low":[118],"voltage":[119],"operations.":[120],"achieves":[124],"more":[125],"than":[126,149],"20-40%":[127],"when":[130],"compared":[131],"to":[132,147],"previous":[133],"generations":[134],"demonstrates":[136],"wide":[137],"operating":[138],"ranges":[139],"from":[140],"1.2":[141],"GHz":[142,151],"at":[143,152],"below":[144],"0.7":[145],"V":[146],"greater":[148],"4.0":[150],"above":[153],"1.0":[154],"V.":[155]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}