{"id":"https://openalex.org/W1972578932","doi":"https://doi.org/10.1109/jssc.2013.2253407","title":"A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique","display_name":"A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique","publication_year":2013,"publication_date":"2013-04-04","ids":{"openalex":"https://openalex.org/W1972578932","doi":"https://doi.org/10.1109/jssc.2013.2253407","mag":"1972578932"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2013.2253407","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2253407","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100661079","display_name":"Hyung Seok Kim","orcid":"https://orcid.org/0000-0003-2386-7945"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hyung Seok Kim","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036573077","display_name":"Carlos Ornelas","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carlos Ornelas","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039602588","display_name":"Kailash Chandrashekar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kailash Chandrashekar","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089718956","display_name":"Dan Shi","orcid":"https://orcid.org/0000-0002-8443-947X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Shi","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061544295","display_name":"Pin-En Su","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pin-en Su","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072673563","display_name":"Paolo Madoglio","orcid":"https://orcid.org/0000-0002-6205-9724"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Madoglio","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023936845","display_name":"W.Y. Li","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W.Y. Li","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058466731","display_name":"Ashoke Ravi","orcid":"https://orcid.org/0000-0001-8302-622X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Ravi","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5100661079"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":2.8373,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.90950041,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"48","issue":"7","first_page":"1721","last_page":"1729"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.8227841854095459},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8093084096908569},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6133396625518799},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5832995772361755},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5726938247680664},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.5409556031227112},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.5401424765586853},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5198826789855957},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.4545208811759949},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.4531552791595459},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.4511031210422516},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.4341754615306854},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.42022639513015747},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.41793206334114075},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41735079884529114},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3302994668483734},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26561272144317627},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.22202914953231812},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22187843918800354},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17399609088897705},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1437670886516571}],"concepts":[{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.8227841854095459},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8093084096908569},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6133396625518799},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5832995772361755},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5726938247680664},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.5409556031227112},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.5401424765586853},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5198826789855957},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.4545208811759949},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.4531552791595459},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.4511031210422516},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.4341754615306854},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.42022639513015747},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.41793206334114075},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41735079884529114},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3302994668483734},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26561272144317627},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.22202914953231812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22187843918800354},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17399609088897705},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1437670886516571},{"id":"https://openalex.org/C120164764","wikidata":"https://www.wikidata.org/wiki/Q705396","display_name":"Variable-frequency oscillator","level":4,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2013.2253407","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2013.2253407","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7900000214576721}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1535027829","https://openalex.org/W2021988103","https://openalex.org/W2062952706","https://openalex.org/W2084208879","https://openalex.org/W2099064239","https://openalex.org/W2103868891","https://openalex.org/W2110675623","https://openalex.org/W2112856903","https://openalex.org/W2128282260","https://openalex.org/W2144429677","https://openalex.org/W2147533202","https://openalex.org/W2152453880","https://openalex.org/W2152685717","https://openalex.org/W2153267648","https://openalex.org/W2164587179","https://openalex.org/W2177833654","https://openalex.org/W2212877209","https://openalex.org/W2280387905","https://openalex.org/W6681793391","https://openalex.org/W6682070686","https://openalex.org/W6682282405"],"related_works":["https://openalex.org/W2013112440","https://openalex.org/W2283201674","https://openalex.org/W2182982459","https://openalex.org/W2253007884","https://openalex.org/W1481111971","https://openalex.org/W2401428732","https://openalex.org/W2952154040","https://openalex.org/W2075683814","https://openalex.org/W2462393914","https://openalex.org/W2220638383"],"abstract_inverted_index":{"A":[0,61],"6-bit":[1],"time-to-digital":[2],"converter":[3],"that":[4],"achieves":[5],"mismatch":[6,82,157],"free":[7],"operation":[8],"by":[9],"using":[10],"a":[11,26,32,47,89,97,104,119],"single":[12],"delay":[13],"cell":[14],"and":[15,50,69,77,158],"sampling":[16],"flip-flop":[17],"is":[18,65,116,149],"presented.":[19],"The":[20,41,86,110,141],"proposed":[21],"TDC":[22,42,76,156],"was":[23],"integrated":[24,124],"in":[25,31,74,99,145],"digital":[27,34,62],"fractional-N":[28],"PLL":[29],"fabricated":[30],"32-nm":[33],"SoC":[35],"CMOS":[36],"process":[37],"for":[38,71],"WiFi/WiMax":[39],"radios.":[40],"consumes":[43],"3":[44],"mW":[45,139],"from":[46,118],"1.05-V":[48],"supply":[49],"occupies":[51],"an":[52,123],"area":[53],"of":[54,127],"0.004":[55],"mm":[56],"<sup":[57],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[58],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[59],".":[60,140],"frequency-locked":[63],"loop":[64],"used":[66],"to":[67,95,101,133],"track":[68],"correct":[70],"PVT":[72],"variations":[73],"the":[75,146],"no":[78],"additional":[79],"linearization":[80],"or":[81],"calibrations":[83],"are":[84],"required.":[85],"DPLL":[87],"uses":[88],"20-bit":[90],"high":[91],"dynamic":[92],"range":[93],"DAC":[94],"drive":[96],"VCO":[98],"order":[100],"effectively":[102],"realize":[103],"DCO":[105],"with":[106,122],"100-Hz":[107],"frequency":[108],"resolution.":[109],"2.5-GHz":[111],"WiFi":[112],"band":[113],"LO":[114,147],"output":[115,148],"generated":[117],"40-MHz":[120],"reference":[121],"phase":[125],"noise":[126],"-":[128,151],"35":[129],"dBc":[130,153],"(10":[131],"kHz":[132],"10":[134],"MHz)":[135],"while":[136],"consuming":[137],"21":[138],"worst":[142],"case":[143],"spur":[144],"below":[150],"50":[152],"without":[154],"requiring":[155],"linearity":[159],"calibration.":[160]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}