{"id":"https://openalex.org/W2025340565","doi":"https://doi.org/10.1109/jssc.2012.2220912","title":"Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction","display_name":"Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction","publication_year":2012,"publication_date":"2012-11-29","ids":{"openalex":"https://openalex.org/W2025340565","doi":"https://doi.org/10.1109/jssc.2012.2220912","mag":"2025340565"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2012.2220912","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2012.2220912","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087082539","display_name":"Matthew Fojtik","orcid":"https://orcid.org/0000-0003-3138-9293"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew Fojtik","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110074219","display_name":"David Fick","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Fick","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077178059","display_name":"Yejoong Kim","orcid":"https://orcid.org/0000-0001-9114-3696"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yejoong Kim","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathaniel Pinckney","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101661944","display_name":"David Harris","orcid":"https://orcid.org/0000-0001-9075-5965"},"institutions":[{"id":"https://openalex.org/I133543626","display_name":"Harvey Mudd College","ror":"https://ror.org/025ecfn45","country_code":"US","type":"education","lineage":["https://openalex.org/I133543626"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Money Harris","raw_affiliation_strings":["Harvey Mudd College, Claremont, CA, USA","Harvey Mudd College Claremont CA USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Harvey Mudd College, Claremont, CA, USA","institution_ids":["https://openalex.org/I133543626"]},{"raw_affiliation_string":"Harvey Mudd College Claremont CA USA","institution_ids":["https://openalex.org/I133543626"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026311377","display_name":"David Blaauw","orcid":"https://orcid.org/0000-0001-6744-7075"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Blaauw","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000767141","display_name":"Dennis Sylvester","orcid":"https://orcid.org/0000-0003-2598-0458"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dennis Sylvester","raw_affiliation_strings":["University of Michigan, Ann Arbor, MI, USA","University of Michigan Ann Arbor MI, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]},{"raw_affiliation_string":"University of Michigan Ann Arbor MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.745,"has_fulltext":false,"cited_by_count":151,"citation_normalized_percentile":{"value":0.9768142,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":"48","issue":"1","first_page":"66","last_page":"81"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.8123462796211243},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7773693799972534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6605994701385498},{"id":"https://openalex.org/keywords/bubble","display_name":"Bubble","score":0.6195171475410461},{"id":"https://openalex.org/keywords/arm-architecture","display_name":"ARM architecture","score":0.5947346687316895},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5682098865509033},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.44008758664131165},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4350307881832123},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38641923666000366},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.23738548159599304},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.222150057554245},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15333575010299683},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1228986382484436}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.8123462796211243},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7773693799972534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6605994701385498},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.6195171475410461},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.5947346687316895},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5682098865509033},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.44008758664131165},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4350307881832123},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38641923666000366},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23738548159599304},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.222150057554245},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15333575010299683},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1228986382484436}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2012.2220912","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2012.2220912","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1541483005","https://openalex.org/W1911029421","https://openalex.org/W1966733028","https://openalex.org/W2009198262","https://openalex.org/W2015917466","https://openalex.org/W2041727850","https://openalex.org/W2069217703","https://openalex.org/W2078174680","https://openalex.org/W2079706534","https://openalex.org/W2086447087","https://openalex.org/W2102587899","https://openalex.org/W2104677471","https://openalex.org/W2105485345","https://openalex.org/W2106648230","https://openalex.org/W2120970098","https://openalex.org/W2133079932","https://openalex.org/W2147458209","https://openalex.org/W2153489710","https://openalex.org/W2156667996","https://openalex.org/W2157465781","https://openalex.org/W2178304595","https://openalex.org/W3141370589","https://openalex.org/W4236432903","https://openalex.org/W6640006728","https://openalex.org/W6652784093","https://openalex.org/W6675621485"],"related_works":["https://openalex.org/W2134549436","https://openalex.org/W233224440","https://openalex.org/W2160236198","https://openalex.org/W1951668625","https://openalex.org/W2903287280","https://openalex.org/W3140976369","https://openalex.org/W2971948178","https://openalex.org/W2306135739","https://openalex.org/W2734397002","https://openalex.org/W2371350567"],"abstract_inverted_index":{"We":[0,44],"propose":[1],"Bubble":[2,46,84],"Razor,":[3],"an":[4,49,110],"architecturally":[5],"independent":[6],"approach":[7],"to":[8,39,41,64,76,122,125],"timing":[9,21,79,130],"error":[10],"detection":[11],"and":[12,18],"correction":[13],"that":[14,28],"avoids":[15],"hold-time":[16],"issues":[17],"enables":[19],"large":[20],"speculation":[22],"windows.":[23],"A":[24],"local":[25],"stalling":[26],"technique":[27],"can":[29],"be":[30],"automatically":[31],"inserted":[32,88],"into":[33],"any":[34],"design":[35,73],"allows":[36],"the":[37,66,95],"system":[38,93],"scale":[40],"larger":[42],"processors.":[43],"implemented":[45],"Razor":[47,85],"on":[48,103],"ARM":[50],"Cortex-M3":[51],"microprocessor":[52],"in":[53],"45":[54],"nm":[55],"CMOS":[56],"without":[57],"detailed":[58],"knowledge":[59],"of":[60,99,114,120],"its":[61],"internal":[62],"architecture":[63],"demonstrate":[65],"technique's":[67],"automated":[68],"capability.":[69],"The":[70],"flip-flop":[71],"based":[72],"was":[74,86],"converted":[75],"two-phase":[77],"latch":[78],"using":[80,89],"commercial":[81,106],"retiming":[82],"tools;":[83],"then":[87],"automatic":[90],"scripts.":[91],"This":[92],"marks":[94],"first":[96],"published":[97],"implementation":[98],"a":[100,104,117],"Razor-style":[101],"scheme":[102],"complete,":[105],"processor.":[107],"It":[108],"provides":[109],"energy":[111],"efficiency":[112],"improvement":[113],"60%":[115],"or":[116],"throughput":[118],"gain":[119],"up":[121],"100%":[123],"compared":[124],"operating":[126],"with":[127],"worst":[128],"case":[129],"margins.":[131]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":14},{"year":2019,"cited_by_count":17},{"year":2018,"cited_by_count":20},{"year":2017,"cited_by_count":26},{"year":2016,"cited_by_count":23},{"year":2015,"cited_by_count":23},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
