{"id":"https://openalex.org/W2156571376","doi":"https://doi.org/10.1109/jssc.2011.2158024","title":"A Programmable Vision Chip Based on Multiple Levels of Parallel Processors","display_name":"A Programmable Vision Chip Based on Multiple Levels of Parallel Processors","publication_year":2011,"publication_date":"2011-07-06","ids":{"openalex":"https://openalex.org/W2156571376","doi":"https://doi.org/10.1109/jssc.2011.2158024","mag":"2156571376"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2011.2158024","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2158024","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101691325","display_name":"Wancheng Zhang","orcid":"https://orcid.org/0000-0002-2039-6431"},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wancheng Zhang","raw_affiliation_strings":["State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015012413","display_name":"Qiuyu Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiuyu Fu","raw_affiliation_strings":["State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110665174","display_name":"Nanjian Wu","orcid":"https://orcid.org/0000-0001-8022-0262"},"institutions":[{"id":"https://openalex.org/I4210149211","display_name":"Institute of Semiconductors","ror":"https://ror.org/048dd0611","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210149211"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Nan-Jian Wu","raw_affiliation_strings":["State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy and Sciences, Beijing, China","institution_ids":["https://openalex.org/I4210149211"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210149211"],"apc_list":null,"apc_paid":null,"fwci":8.6494,"has_fulltext":false,"cited_by_count":91,"citation_normalized_percentile":{"value":0.98028075,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":100},"biblio":{"volume":"46","issue":"9","first_page":"2132","last_page":"2147"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12236","display_name":"Photoreceptor and optogenetics research","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.9185436367988586},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7247315645217896},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6505407691001892},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6182446479797363},{"id":"https://openalex.org/keywords/parallel-processing","display_name":"Parallel processing","score":0.6076595187187195},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.5631409883499146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.513384222984314},{"id":"https://openalex.org/keywords/processor-array","display_name":"Processor array","score":0.48890796303749084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4828830063343048},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.4738926291465759},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4572224020957947},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.4439064562320709},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.25855737924575806},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.22990798950195312},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12386709451675415},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.0915529727935791}],"concepts":[{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.9185436367988586},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7247315645217896},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6505407691001892},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6182446479797363},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.6076595187187195},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.5631409883499146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.513384222984314},{"id":"https://openalex.org/C2776189500","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Processor array","level":2,"score":0.48890796303749084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4828830063343048},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4738926291465759},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4572224020957947},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.4439064562320709},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.25855737924575806},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.22990798950195312},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12386709451675415},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0915529727935791},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2011.2158024","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2158024","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W158072590","https://openalex.org/W201442221","https://openalex.org/W1528444979","https://openalex.org/W1563614423","https://openalex.org/W1587952852","https://openalex.org/W1597755753","https://openalex.org/W2019156749","https://openalex.org/W2049905908","https://openalex.org/W2051866379","https://openalex.org/W2083770087","https://openalex.org/W2093719511","https://openalex.org/W2097988027","https://openalex.org/W2098034272","https://openalex.org/W2098284001","https://openalex.org/W2098602075","https://openalex.org/W2106248457","https://openalex.org/W2111730644","https://openalex.org/W2113491211","https://openalex.org/W2117148079","https://openalex.org/W2117470539","https://openalex.org/W2119089459","https://openalex.org/W2120339890","https://openalex.org/W2122066961","https://openalex.org/W2125430715","https://openalex.org/W2127311482","https://openalex.org/W2129150326","https://openalex.org/W2129996759","https://openalex.org/W2136401082","https://openalex.org/W2145324087","https://openalex.org/W2148679215","https://openalex.org/W2155529599","https://openalex.org/W2162816583","https://openalex.org/W2163594386","https://openalex.org/W2171843744","https://openalex.org/W2176428682","https://openalex.org/W2567052870","https://openalex.org/W2685631283","https://openalex.org/W3023595663","https://openalex.org/W4256068510","https://openalex.org/W4285719527","https://openalex.org/W6663494093"],"related_works":["https://openalex.org/W2766828645","https://openalex.org/W2065177255","https://openalex.org/W2013845618","https://openalex.org/W196565075","https://openalex.org/W1667038987","https://openalex.org/W2117894653","https://openalex.org/W2167865373","https://openalex.org/W2038729084","https://openalex.org/W2156571376","https://openalex.org/W2096870795"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,49],"novel":[4],"programmable":[5],"vision":[6,111,114,123],"chip":[7,16,115,141],"based":[8],"on":[9],"multiple":[10],"levels":[11],"of":[12,22,34,39,43,51,109,121],"parallel":[13,24,36],"processors.":[14],"The":[15,32,56,72,89,113],"integrates":[17],"CMOS":[18,165],"image":[19,100,127,137,146,174],"sensor,":[20,147],"multiple-levels":[21,33],"SIMD":[23,35,44,52],"processors":[25,37,54],"and":[26,48,59,67,75,86,93,132,154,173],"an":[27,40,62,68],"embedded":[28],"microprocessor":[29],"unit":[30],"(MPU).":[31],"consist":[38],"array":[41,58,74],"processor":[42],"processing":[45,87,101],"elements":[46],"(PEs)":[47],"column":[50],"row":[53],"(RPs).":[55],"PE":[57,73,90],"RPs":[60,76,92,153],"have":[61],"O(N":[63],"\u00d7":[64,144,156],"N)":[65],"parallelism":[66],"O(N)":[69],"parallelism,":[70],"respectively.":[71],"can":[77,95,116],"be":[78],"reconfigured":[79],"to":[80],"handle":[81],"algorithms":[82],"with":[83,142],"different":[84,122],"complexities":[85],"speeds.":[88],"array,":[91],"MPU":[94],"execute":[96],"low-,":[97],"mid-and":[98],"high-level":[99],"algorithms,":[102],"respectively,":[103],"which":[104],"efficiently":[105],"increases":[106],"the":[107,110,119,162],"performance":[108],"chip.":[112],"satisfy":[117],"flexibly":[118],"needs":[120],"applications":[124],"such":[125],"as":[126],"pre-processing,":[128],"complicated":[129],"feature":[130],"extraction":[131,172],"over":[133],"1000":[134],"fps":[135],"high-speed":[136],"capture.":[138],"A":[139],"prototype":[140],"128":[143,148,157],"28":[145],"A/D":[149],"converters,":[150],"32":[151,155],"8-bit":[152],"PEs":[158],"is":[159],"fabricated":[160],"using":[161],"0.18":[163],"\u03bcm":[164],"process.":[166],"Applications":[167],"including":[168],"target":[169],"tracking,":[170],"pattern":[171],"recognition":[175],"are":[176],"demonstrated.":[177]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":8},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":13},{"year":2014,"cited_by_count":16},{"year":2013,"cited_by_count":12},{"year":2012,"cited_by_count":4}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
