{"id":"https://openalex.org/W2099701416","doi":"https://doi.org/10.1109/jssc.2011.2148430","title":"Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory","display_name":"Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory","publication_year":2011,"publication_date":"2011-06-07","ids":{"openalex":"https://openalex.org/W2099701416","doi":"https://doi.org/10.1109/jssc.2011.2148430","mag":"2099701416"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2011.2148430","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2148430","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010964466","display_name":"E. Ou","orcid":"https://orcid.org/0000-0002-7935-8288"},"institutions":[{"id":"https://openalex.org/I129604602","display_name":"The University of Sydney","ror":"https://ror.org/0384j8v12","country_code":"AU","type":"education","lineage":["https://openalex.org/I129604602"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Elaine Ou","raw_affiliation_strings":["Department of Electrical and Information Engineering, University of Sydney, NSW, Australia","Dept. of Electr. & Inf. Eng., Univ. of Sydney, Sydney, NSW, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Information Engineering, University of Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]},{"raw_affiliation_string":"Dept. of Electr. & Inf. Eng., Univ. of Sydney, Sydney, NSW, Australia","institution_ids":["https://openalex.org/I129604602"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066440288","display_name":"S.S. Wong","orcid":"https://orcid.org/0000-0003-4361-1744"},"institutions":[{"id":"https://openalex.org/I4210160740","display_name":"Integrated Software (United States)","ror":"https://ror.org/05dp7m259","country_code":"US","type":"company","lineage":["https://openalex.org/I4210160740"]},{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Simon Wong","raw_affiliation_strings":["Center of Integrated Systems, University of Stanford, Stanford, CA, USA","Center for Integrated Syst., Stanford Univ., Stanford, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center of Integrated Systems, University of Stanford, Stanford, CA, USA","institution_ids":[]},{"raw_affiliation_string":"Center for Integrated Syst., Stanford Univ., Stanford, CA, USA","institution_ids":["https://openalex.org/I4210160740","https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.1654,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.8144226,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"46","issue":"9","first_page":"2158","last_page":"2170"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6875628232955933},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.6736183166503906},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5645242929458618},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5527997612953186},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5411469340324402},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5095003247261047},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4939780831336975},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.47372308373451233},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.4534755051136017},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4510211646556854},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43937426805496216},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.4311336576938629},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.42377984523773193},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38854190707206726},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3879584074020386},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37477707862854004},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32933294773101807},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24371293187141418},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20343416929244995},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.17765823006629944},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13524174690246582}],"concepts":[{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6875628232955933},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.6736183166503906},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5645242929458618},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5527997612953186},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5411469340324402},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5095003247261047},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4939780831336975},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.47372308373451233},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.4534755051136017},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4510211646556854},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43937426805496216},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.4311336576938629},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.42377984523773193},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38854190707206726},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3879584074020386},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37477707862854004},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32933294773101807},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24371293187141418},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20343416929244995},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.17765823006629944},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13524174690246582},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2011.2148430","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2148430","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.75}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1481988107","https://openalex.org/W1486495540","https://openalex.org/W1801702371","https://openalex.org/W1964056440","https://openalex.org/W1982435996","https://openalex.org/W1985604842","https://openalex.org/W2032091965","https://openalex.org/W2051736202","https://openalex.org/W2052677323","https://openalex.org/W2085273892","https://openalex.org/W2091201490","https://openalex.org/W2091727519","https://openalex.org/W2141161586","https://openalex.org/W2142595917","https://openalex.org/W2147667149","https://openalex.org/W2543638529","https://openalex.org/W4254007354","https://openalex.org/W6641072724","https://openalex.org/W6647057901"],"related_works":["https://openalex.org/W2898989424","https://openalex.org/W2185519377","https://openalex.org/W4285257158","https://openalex.org/W2505369450","https://openalex.org/W2171888576","https://openalex.org/W4293159259","https://openalex.org/W2473964774","https://openalex.org/W1494152240","https://openalex.org/W2150506489","https://openalex.org/W2615320339"],"abstract_inverted_index":{"This":[0,40,107],"work":[1,41],"explores":[2],"the":[3,26,30,34,70,109],"design":[4],"and":[5,29,45,72,122],"capabilities":[6],"of":[7,77,95,104,119,129],"a":[8,55,101],"three-dimensional":[9],"cross-point":[10,111],"array":[11],"structure":[12],"suitable":[13],"for":[14,36],"use":[15],"with":[16,100,114,124],"resistance-change":[17,21],"non-volatile":[18],"memory.":[19],"The":[20,75],"cell":[22],"serves":[23],"as":[24],"both":[25],"access":[27,93],"element":[28],"memory":[31,81,112],"element,":[32],"eliminating":[33],"need":[35],"individual":[37],"selection":[38],"devices.":[39],"presents":[42],"novel":[43],"architecture":[44,71],"circuit":[46,73],"techniques":[47],"that":[48],"minimize":[49],"leakage":[50],"current":[51],"effects":[52],"while":[53],"maintaining":[54],"high":[56],"effective":[57],"bit":[58],"density.":[59],"A":[60,91],"test":[61],"chip":[62,82],"fabricated":[63],"in":[64,84,117,127],"0.18":[65],"\u03bcm":[66],"CMOS":[67],"technology":[68,87],"verifies":[69],"functionality.":[74],"performance":[76],"an":[78],"8":[79],"Gb":[80],"built":[83],"65":[85],"nm":[86],"has":[88],"been":[89],"simulated.":[90],"random":[92],"time":[94],"104":[96],"ns":[97],"is":[98],"achieved":[99],"power":[102],"dissipation":[103],"61.2":[105],"mW.":[106],"makes":[108],"3D":[110],"competitive":[113,123],"NOR":[115],"flash":[116,126],"terms":[118,128],"read":[120],"time,":[121],"NAND":[125],"area":[130],"efficiency.":[131]},"counts_by_year":[{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}