{"id":"https://openalex.org/W2125528964","doi":"https://doi.org/10.1109/jssc.2011.2145290","title":"A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-$\\mu$m SiGe BiCMOS","display_name":"A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35-$\\mu$m SiGe BiCMOS","publication_year":2011,"publication_date":"2011-06-07","ids":{"openalex":"https://openalex.org/W2125528964","doi":"https://doi.org/10.1109/jssc.2011.2145290","mag":"2125528964"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2011.2145290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2145290","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066897196","display_name":"Ching\u2010Yuan Yang","orcid":"https://orcid.org/0000-0002-5335-3665"},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Yuan Yang","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","institution_ids":["https://openalex.org/I162838928"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023812603","display_name":"Jun-Hong Weng","orcid":null},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jun-Hong Weng","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","institution_ids":["https://openalex.org/I162838928"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049900529","display_name":"Hsuan-Yu Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I162838928","display_name":"National Chung Hsing University","ror":"https://ror.org/05vn3ca78","country_code":"TW","type":"education","lineage":["https://openalex.org/I162838928"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsuan-Yu Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, R.O.C","institution_ids":["https://openalex.org/I162838928"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Chung Hsing Univ., Taichung, Taiwan","institution_ids":["https://openalex.org/I162838928"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162838928"],"apc_list":null,"apc_paid":null,"fwci":2.5567,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.89956715,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"46","issue":"9","first_page":"2064","last_page":"2072"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.9265506863594055},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.68290776014328},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.6768039464950562},{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.6419580578804016},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5994867086410522},{"id":"https://openalex.org/keywords/sine-wave","display_name":"Sine wave","score":0.5747994184494019},{"id":"https://openalex.org/keywords/nyquist\u2013shannon-sampling-theorem","display_name":"Nyquist\u2013Shannon sampling theorem","score":0.5238085985183716},{"id":"https://openalex.org/keywords/digital-to-analog-converter","display_name":"Digital-to-analog converter","score":0.5207222104072571},{"id":"https://openalex.org/keywords/sine","display_name":"Sine","score":0.4859555959701538},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.47504758834838867},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42806389927864075},{"id":"https://openalex.org/keywords/nyquist-frequency","display_name":"Nyquist frequency","score":0.4226928949356079},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.41065841913223267},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.36063989996910095},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.33605629205703735},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.30833667516708374},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2453083097934723},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.22996270656585693},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19931846857070923},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.18324536085128784}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.9265506863594055},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.68290776014328},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.6768039464950562},{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.6419580578804016},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5994867086410522},{"id":"https://openalex.org/C66907618","wikidata":"https://www.wikidata.org/wiki/Q207527","display_name":"Sine wave","level":3,"score":0.5747994184494019},{"id":"https://openalex.org/C288623","wikidata":"https://www.wikidata.org/wiki/Q679800","display_name":"Nyquist\u2013Shannon sampling theorem","level":2,"score":0.5238085985183716},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.5207222104072571},{"id":"https://openalex.org/C186661526","wikidata":"https://www.wikidata.org/wiki/Q13647261","display_name":"Sine","level":2,"score":0.4859555959701538},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.47504758834838867},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42806389927864075},{"id":"https://openalex.org/C98273374","wikidata":"https://www.wikidata.org/wiki/Q1501757","display_name":"Nyquist frequency","level":3,"score":0.4226928949356079},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.41065841913223267},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.36063989996910095},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.33605629205703735},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.30833667516708374},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2453083097934723},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.22996270656585693},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19931846857070923},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.18324536085128784},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2011.2145290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2011.2145290","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1489252058","https://openalex.org/W2013402967","https://openalex.org/W2021949203","https://openalex.org/W2051493063","https://openalex.org/W2098156200","https://openalex.org/W2100585207","https://openalex.org/W2100721998","https://openalex.org/W2101021701","https://openalex.org/W2102254452","https://openalex.org/W2108375504","https://openalex.org/W2115511191","https://openalex.org/W2123509731","https://openalex.org/W2140576958","https://openalex.org/W2141492992","https://openalex.org/W2153329815","https://openalex.org/W2155125045","https://openalex.org/W2159386728","https://openalex.org/W2164621514","https://openalex.org/W2164914331","https://openalex.org/W2171048287","https://openalex.org/W2971193830","https://openalex.org/W4248775349"],"related_works":["https://openalex.org/W2166555237","https://openalex.org/W2161572852","https://openalex.org/W2622028395","https://openalex.org/W3021352409","https://openalex.org/W2087722618","https://openalex.org/W2163754102","https://openalex.org/W2106844041","https://openalex.org/W2342609974","https://openalex.org/W2528390758","https://openalex.org/W2124912300"],"abstract_inverted_index":{"A":[0],"direct":[1],"digital":[2],"frequency":[3,77,114,117],"synthesizer":[4],"(DDFS)":[5],"using":[6],"an":[7],"analog-sine-mapping":[8],"technique":[9],"is":[10,41,95],"presented":[11],"in":[12],"a":[13,27,127,132],"0.35-\u03bcm":[14],"SiGe":[15],"BiCMOS":[16],"process.":[17],"We":[18],"intend":[19],"to":[20,25,46,50,105],"apply":[21],"the":[22,44,57,93,111],"translinear":[23],"principle":[24],"develop":[26],"triangle-to-sine":[28],"converter":[29],"(TSC)":[30],"that":[31],"can":[32,71,79],"achieve":[33,72],"outputs":[34],"with":[35,59],"low":[36,101],"harmonic":[37],"content.":[38],"The":[39,87,121,143],"TSC":[40],"introduced":[42],"for":[43,115],"DDFS":[45,94,122],"translate":[47],"phase":[48,63],"data":[49],"sine":[51],"wave.":[52],"Using":[53],"this":[54],"analog-interpolating":[55],"technique,":[56],"DDFS,":[58],"9":[60],"bits":[61,67],"of":[62,68,92,137,140],"resolution":[64],"and":[65,78,84,130],"8":[66],"amplitude":[69],"resolution,":[70],"operation":[73],"at":[74,100,110,126],"5-GHz":[75],"clock":[76],"further":[80],"reduce":[81],"power":[82,134],"consumption":[83],"die":[85],"area.":[86],"spurious-free":[88],"dynamic":[89],"range":[90],"(SFDR)":[91],"better":[96],"than":[97],"48":[98],"dBc":[99,107],"synthesized":[102,113],"frequencies,":[103],"decreasing":[104],"45.7":[106],"worst":[108],"case":[109],"Nyquist":[112],"output":[116],"band":[118],"(0-2.5":[119],"GHz).":[120],"consumes":[123],"460":[124],"mW":[125],"3.3-V":[128],"supply":[129],"achieves":[131],"high":[133],"efficiency":[135],"figure":[136],"merit":[138],"(FOM)":[139],"10.87":[141],"GHz/W.":[142],"chip":[144],"occupies":[145],"1.5":[146],"\u00d7":[147],"1.4":[148],"mm2.":[149]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}