{"id":"https://openalex.org/W2131053965","doi":"https://doi.org/10.1109/jssc.2010.2053094","title":"Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector","display_name":"Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector","publication_year":2010,"publication_date":"2010-08-24","ids":{"openalex":"https://openalex.org/W2131053965","doi":"https://doi.org/10.1109/jssc.2010.2053094","mag":"2131053965"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2010.2053094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2010.2053094","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://ris.utwente.nl/ws/files/6782511/Gao_IEEE_JSSC_sept_2010.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049999335","display_name":"Xiang Gao","orcid":"https://orcid.org/0000-0003-2890-061X"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Xiang Gao","raw_affiliation_strings":["IC-Design group, University of Twente, Enschede, Netherlands","IC-Design group, Univ. of Twente, Enschede, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC-Design group, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"IC-Design group, Univ. of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023038843","display_name":"Eric A.M. Klumperink","orcid":"https://orcid.org/0000-0003-2487-8996"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Eric A. M. Klumperink","raw_affiliation_strings":["IC-Design group, University of Twente, Enschede, Netherlands","IC-Design group, Univ. of Twente, Enschede, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC-Design group, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"IC-Design group, Univ. of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080523927","display_name":"Gerard Socci","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gerard Socci","raw_affiliation_strings":["National Semiconductor Corporation, Santa Clara, CA, USA","Nat. Semicond., Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Semiconductor Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Nat. Semicond., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061692135","display_name":"Mounir Bohsali","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mounir Bohsali","raw_affiliation_strings":["National Semiconductor Corporation, Santa Clara, CA, USA","Nat. Semicond., Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Semiconductor Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I74760111"]},{"raw_affiliation_string":"Nat. Semicond., Santa Clara, CA, USA","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035402438","display_name":"Bram Nauta","orcid":"https://orcid.org/0000-0001-6790-5873"},"institutions":[{"id":"https://openalex.org/I94624287","display_name":"University of Twente","ror":"https://ror.org/006hf6230","country_code":"NL","type":"education","lineage":["https://openalex.org/I94624287"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Bram Nauta","raw_affiliation_strings":["IC-Design group, University of Twente, Enschede, Netherlands","IC-Design group, Univ. of Twente, Enschede, Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC-Design group, University of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]},{"raw_affiliation_string":"IC-Design group, Univ. of Twente, Enschede, Netherlands","institution_ids":["https://openalex.org/I94624287"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.8253,"has_fulltext":true,"cited_by_count":168,"citation_normalized_percentile":{"value":0.93709351,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"45","issue":"9","first_page":"1809","last_page":"1821"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.8937646150588989},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8624920845031738},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.8157800436019897},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6524105668067932},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.6096569299697876},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6093463897705078},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.5816980600357056},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5161610245704651},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.5071656703948975},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48634058237075806},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4546814262866974},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.43609875440597534},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.41023704409599304},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.34765303134918213},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.30132150650024414},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3010828495025635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2413094937801361},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23380833864212036},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13437438011169434},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.09851741790771484}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.8937646150588989},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8624920845031738},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.8157800436019897},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6524105668067932},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.6096569299697876},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6093463897705078},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.5816980600357056},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5161610245704651},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5071656703948975},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48634058237075806},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4546814262866974},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.43609875440597534},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.41023704409599304},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.34765303134918213},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.30132150650024414},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3010828495025635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2413094937801361},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23380833864212036},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13437438011169434},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.09851741790771484},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/jssc.2010.2053094","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2010.2053094","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},{"id":"pmh:oai:ris.utwente.nl:publications/2fa94b53-bcde-4b76-abe7-61a66d2c2a2b","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/2fa94b53-bcde-4b76-abe7-61a66d2c2a2b","pdf_url":"https://ris.utwente.nl/ws/files/6782511/Gao_IEEE_JSSC_sept_2010.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"Gao, X, Klumperink, E A M, Socci, G, Bohsali, M & Nauta, B 2010, 'Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector', IEEE journal of solid-state circuits, vol. 45, no. 9, pp. 1809-1821. https://doi.org/10.1109/JSSC.2010.2053094","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"pmh:oai:ris.utwente.nl:publications/2fa94b53-bcde-4b76-abe7-61a66d2c2a2b","is_oa":true,"landing_page_url":"https://research.utwente.nl/en/publications/2fa94b53-bcde-4b76-abe7-61a66d2c2a2b","pdf_url":"https://ris.utwente.nl/ws/files/6782511/Gao_IEEE_JSSC_sept_2010.pdf","source":{"id":"https://openalex.org/S4406922991","display_name":"University of Twente Research Information","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"Gao, X, Klumperink, E A M, Socci, G, Bohsali, M & Nauta, B 2010, 'Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector', IEEE journal of solid-state circuits, vol. 45, no. 9, pp. 1809-1821. https://doi.org/10.1109/JSSC.2010.2053094","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"score":0.4399999976158142,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2131053965.pdf","grobid_xml":"https://content.openalex.org/works/W2131053965.grobid-xml"},"referenced_works_count":24,"referenced_works":["https://openalex.org/W575489327","https://openalex.org/W634962531","https://openalex.org/W1620633355","https://openalex.org/W1965174157","https://openalex.org/W2000068870","https://openalex.org/W2002519749","https://openalex.org/W2007981967","https://openalex.org/W2028717752","https://openalex.org/W2033908335","https://openalex.org/W2085732029","https://openalex.org/W2097406868","https://openalex.org/W2100957399","https://openalex.org/W2102596261","https://openalex.org/W2102745850","https://openalex.org/W2107514446","https://openalex.org/W2118269375","https://openalex.org/W2123109015","https://openalex.org/W2139110107","https://openalex.org/W2150524153","https://openalex.org/W2150912637","https://openalex.org/W2158535017","https://openalex.org/W2165238044","https://openalex.org/W2167891824","https://openalex.org/W2177833654"],"related_works":["https://openalex.org/W3093724499","https://openalex.org/W2213169543","https://openalex.org/W2062737926","https://openalex.org/W2369807905","https://openalex.org/W2979324006","https://openalex.org/W4385624389","https://openalex.org/W1504159650","https://openalex.org/W4381745543","https://openalex.org/W2087564251","https://openalex.org/W2558244976"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"phase-locked":[3],"loop":[4,102],"(PLL)":[5],"reference-spur":[6],"reduction":[7,123],"design":[8],"techniques":[9],"exploiting":[10],"a":[11,22,36,125,140],"sub-sampling":[12],"phase":[13,24,165],"detector":[14],"(SSPD)":[15],"(which":[16],"is":[17,28,45,48,62,87,129,153,167,184],"also":[18],"referred":[19],"to":[20,51,107,181],"as":[21],"sampling":[23,71,79],"detector).":[25],"The":[26,53,76,157],"VCO":[27,59,68,78],"sampled":[29],"by":[30,69,89],"the":[31,58,63,67,70,73,110,117,120,146,163,174],"reference":[32,60,74,98,147],"clock":[33],"without":[34],"using":[35,90,139],"frequency":[37],"divider":[38],"and":[39,84,93,100,131,173],"an":[40],"amplitude":[41],"controlled":[42],"charge":[43],"pump":[44],"used":[46],"which":[47],"inherently":[49],"insensitive":[50],"mismatch.":[52],"main":[54],"remaining":[55],"source":[56],"of":[57,66,119,144],"spur":[61,80,113,122,148],"periodic":[64],"disturbance":[65],"at":[72,170],"frequency.":[75],"underlying":[77],"mechanisms":[81],"are":[82,105],"analyzed":[83],"their":[85],"effect":[86],"minimized":[88],"dummy":[91],"samplers":[92],"isolation":[94],"buffers.":[95],"A":[96],"duty-cycle-controlled":[97],"buffer":[99],"delay-locked":[101],"(DLL)":[103],"tuning":[104],"proposed":[106,121],"further":[108],"reduce":[109],"worst":[111],"case":[112],"level.":[114],"To":[115],"demonstrate":[116],"effectiveness":[118],"techniques,":[124],"2.21":[126],"GHz":[127],"PLL":[128,158],"designed":[130],"fabricated":[132],"in":[133],"0.18":[134],"\u03bcm":[135],"CMOS":[136],"technology.":[137],"While":[138],"high":[141],"loop-bandwidth-to-reference-frequency":[142],"ratio":[143],"1/20,":[145],"measured":[149],"from":[150,178],"20":[151],"chips":[152],"<;":[154],"-80":[155],"dBc.":[156],"consumes":[159],"3.8":[160],"mW":[161],"while":[162],"in-band":[164],"noise":[166],"-121":[168],"dBc/Hz":[169],"200":[171],"kHz":[172,180],"output":[175],"jitter":[176],"integrated":[177],"10":[179],"100":[182],"MHz":[183],"0.3ps":[185],"<sub":[186],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[187],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rms</sub>":[188],".":[189]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":16},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":24},{"year":2022,"cited_by_count":17},{"year":2021,"cited_by_count":19},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":15},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":6}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}