{"id":"https://openalex.org/W2101339656","doi":"https://doi.org/10.1109/jssc.2009.2025344","title":"Energy\u2013Performance Tunable Logic","display_name":"Energy\u2013Performance Tunable Logic","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2101339656","doi":"https://doi.org/10.1109/jssc.2009.2025344","mag":"2101339656"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2009.2025344","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2025344","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004788307","display_name":"Bita Nezamfar","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Bita Nezamfar","raw_affiliation_strings":["Atheros Communications, Inc., Santa Clara, CA, USA","Stanford University Stanford, CA, USA"],"affiliations":[{"raw_affiliation_string":"Atheros Communications, Inc., Santa Clara, CA, USA","institution_ids":[]},{"raw_affiliation_string":"Stanford University Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038042435","display_name":"Elad Alon","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elad Alon","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Berkeley, CA, USA","[Department of Electrical Engineering, University of California, Berkeley, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"[Department of Electrical Engineering, University of California, Berkeley, CA, USA]","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Horowitz","raw_affiliation_strings":["Department of Electrical Engineering, University of Stanford, Stanford, CA, USA","[Department of Electrical Engineering, University of Stanford, Stanford, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"[Department of Electrical Engineering, University of Stanford, Stanford, CA, USA]","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5004788307"],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.63215299,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"44","issue":"9","first_page":"2554","last_page":"2567"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6196414232254028},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6123895645141602},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5624778866767883},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5248741507530212},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5114444494247437},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4826284348964691},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.46982717514038086},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.46099475026130676},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.45963650941848755},{"id":"https://openalex.org/keywords/pull-up-resistor","display_name":"Pull-up resistor","score":0.45732179284095764},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4238879084587097},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.35897496342658997},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3495023846626282},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2970627546310425}],"concepts":[{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6196414232254028},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6123895645141602},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5624778866767883},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5248741507530212},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5114444494247437},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4826284348964691},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.46982717514038086},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.46099475026130676},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.45963650941848755},{"id":"https://openalex.org/C61818909","wikidata":"https://www.wikidata.org/wiki/Q1987617","display_name":"Pull-up resistor","level":5,"score":0.45732179284095764},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4238879084587097},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.35897496342658997},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3495023846626282},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2970627546310425}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2009.2025344","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2025344","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W1481987700","https://openalex.org/W1803471516","https://openalex.org/W1990333166","https://openalex.org/W2012595012","https://openalex.org/W2016748970","https://openalex.org/W2037921569","https://openalex.org/W2041727850","https://openalex.org/W2045617353","https://openalex.org/W2050589795","https://openalex.org/W2064169027","https://openalex.org/W2075086017","https://openalex.org/W2078835261","https://openalex.org/W2085583524","https://openalex.org/W2088072859","https://openalex.org/W2102587899","https://openalex.org/W2104677471","https://openalex.org/W2105597240","https://openalex.org/W2107766185","https://openalex.org/W2115706095","https://openalex.org/W2117897185","https://openalex.org/W2123654193","https://openalex.org/W2127936519","https://openalex.org/W2131941931","https://openalex.org/W2133079932","https://openalex.org/W2150526221","https://openalex.org/W2160423692","https://openalex.org/W2165079392","https://openalex.org/W2170444169","https://openalex.org/W2288998059","https://openalex.org/W4236432903","https://openalex.org/W4243835011","https://openalex.org/W4285719527","https://openalex.org/W6683961774"],"related_works":["https://openalex.org/W2580743037","https://openalex.org/W2152533674","https://openalex.org/W2114346412","https://openalex.org/W2098419840","https://openalex.org/W1900707063","https://openalex.org/W3023368799","https://openalex.org/W2526300902","https://openalex.org/W2965791759","https://openalex.org/W2159448561","https://openalex.org/W2988242922"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,57,79,101],"new":[3],"logic":[4,54],"family":[5,55],"that":[6,65],"enables":[7],"the":[8,12,42,70,74,90,123],"user":[9],"to":[10,78,100,122],"tune":[11],"transistor's":[13],"effective":[14],"threshold":[15],"voltage":[16,30,85],"after":[17],"fabrication":[18],"for":[19],"higher":[20],"speed":[21],"or":[22],"lower":[23],"power.":[24],"This":[25],"technique":[26],"along":[27],"with":[28],"dynamic":[29,38],"scaling":[31],"allows":[32],"simultaneous":[33],"optimization":[34],"of":[35,89],"static":[36,116],"and":[37],"power":[39],"based":[40],"on":[41,56],"application/workload":[43],"requirements.":[44],"Programmable":[45],"interconnect":[46,81],"from":[47],"an":[48,107],"FPGA":[49],"was":[50],"implemented":[51],"using":[52],"this":[53,66,93],"90":[58],"nm":[59],"CMOS":[60],"test":[61],"chip.":[62],"Measurements":[63],"show":[64],"topology":[67,112],"provides":[68],"twice":[69],"tuning":[71],"range":[72],"in":[73],"energy-performance":[75],"space":[76],"compared":[77,99],"conventional":[80],"utilizing":[82],"only":[83],"supply":[84],"scaling.":[86],"For":[87],"most":[88],"performance":[91],"range,":[92],"circuit":[94,105],"consumes":[95],"35%":[96],"less":[97],"energy":[98],"state-of-the-art":[102],"design.":[103],"The":[104],"is":[106],"externally":[108],"static,":[109],"internally":[110],"pulse-mode":[111],"which":[113],"can":[114],"replace":[115],"circuits":[117],"without":[118],"requiring":[119],"significant":[120],"changes":[121],"system.":[124]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}