{"id":"https://openalex.org/W2128347794","doi":"https://doi.org/10.1109/jssc.2009.2021913","title":"A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS","display_name":"A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS","publication_year":2009,"publication_date":"2009-06-25","ids":{"openalex":"https://openalex.org/W2128347794","doi":"https://doi.org/10.1109/jssc.2009.2021913","mag":"2128347794"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2009.2021913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2021913","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053898533","display_name":"Lucio Rodoni","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Lucio Rodoni","raw_affiliation_strings":["Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","[Electron. Lab., ETH Zurich, Zurich]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","institution_ids":[]},{"raw_affiliation_string":"[Electron. Lab., ETH Zurich, Zurich]","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111971214","display_name":"G. von Buren","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"George von Buren","raw_affiliation_strings":["Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","[Electron. Lab., ETH Zurich, Zurich]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","institution_ids":[]},{"raw_affiliation_string":"[Electron. Lab., ETH Zurich, Zurich]","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045711101","display_name":"Alexander Huber","orcid":"https://orcid.org/0000-0002-8888-8483"},"institutions":[{"id":"https://openalex.org/I2972652528","display_name":"FHNW University of Applied Sciences and Arts Northwestern Switzerland","ror":"https://ror.org/04mq2g308","country_code":"CH","type":"education","lineage":["https://openalex.org/I2972652528"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Alex Huber","raw_affiliation_strings":["Institute of Microelectronics, University of Applied Science, Windisch, Switzerland","[Institute of Microelectronics, University of Applied Science, Windisch, Switzerland]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, University of Applied Science, Windisch, Switzerland","institution_ids":["https://openalex.org/I2972652528"]},{"raw_affiliation_string":"[Institute of Microelectronics, University of Applied Science, Windisch, Switzerland]","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086672126","display_name":"Martin Schmatz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210126328","display_name":"IBM Research - Zurich","ror":"https://ror.org/02js37d36","country_code":"CH","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210126328"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Martin Schmatz","raw_affiliation_strings":["Zurich Research Laboratory, IBM Research GmbH, Ruschlikon, Switzerland","Z\u00fcrich Research laboratory, IBM Research GmbH, R\u00fcschlikon, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Zurich Research Laboratory, IBM Research GmbH, Ruschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]},{"raw_affiliation_string":"Z\u00fcrich Research laboratory, IBM Research GmbH, R\u00fcschlikon, Switzerland","institution_ids":["https://openalex.org/I4210126328"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062689500","display_name":"H. J\u00e4ckel","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Heinz Jackel","raw_affiliation_strings":["Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","[Electron. Lab., ETH Zurich, Zurich]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Laboratory, Swiss Federal Institute of Technology, Zurich, Switzerland","institution_ids":[]},{"raw_affiliation_string":"[Electron. Lab., ETH Zurich, Zurich]","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3795,"has_fulltext":false,"cited_by_count":68,"citation_normalized_percentile":{"value":0.88691452,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":"44","issue":"7","first_page":"1927","last_page":"1941"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7160574793815613},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6129404306411743},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.47882014513015747},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4658893644809723},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3161572813987732},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16304215788841248},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13170704245567322}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7160574793815613},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6129404306411743},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47882014513015747},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4658893644809723},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3161572813987732},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16304215788841248},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13170704245567322}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2009.2021913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2021913","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1494885616","https://openalex.org/W1548579702","https://openalex.org/W1573954521","https://openalex.org/W1599994156","https://openalex.org/W1963587303","https://openalex.org/W1969699488","https://openalex.org/W1977390134","https://openalex.org/W2021362216","https://openalex.org/W2070413034","https://openalex.org/W2075078552","https://openalex.org/W2097937316","https://openalex.org/W2103845095","https://openalex.org/W2105696031","https://openalex.org/W2110286059","https://openalex.org/W2112489816","https://openalex.org/W2114953806","https://openalex.org/W2118935121","https://openalex.org/W2120651488","https://openalex.org/W2124390946","https://openalex.org/W2129669849","https://openalex.org/W2131853386","https://openalex.org/W2132897890","https://openalex.org/W2134687611","https://openalex.org/W2136801359","https://openalex.org/W2145488467","https://openalex.org/W2145923236","https://openalex.org/W2147723792","https://openalex.org/W2166984288","https://openalex.org/W2170215783","https://openalex.org/W2176473673","https://openalex.org/W2176869677","https://openalex.org/W2179048947","https://openalex.org/W2303012689","https://openalex.org/W2306738904","https://openalex.org/W2799067801","https://openalex.org/W2987233715","https://openalex.org/W6629625049","https://openalex.org/W6634510192"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W2058044441","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2109445684"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,39,47,108,125,134,157,164,203],"quarter-rate":[4],"clock":[5,76,86,137],"and":[6,73,112,133,138],"data":[7,30,48,53,93,132,169,195],"recovery":[8],"(CDR)":[9],"circuit":[10],"for":[11,68,185,187],"plesiochronous":[12],"serial":[13,190],"I/O-links.":[14],"The":[15,99,119,200],"2$\\times$-oversampling":[16],"phase-tracking":[17,100],"CDR,":[18],"implemented":[19],"in":[20,38],"90$\\,$nm":[21],"bulk":[22],"CMOS":[23,189],"technology,":[24],"covers":[25],"the":[26,43,91,103,140,175,178,181,193],"whole":[27],"range":[28],"of":[29,46,102,171,180,197,206],"rates":[31],"from":[32],"5.75":[33],"to":[34,90,123,153],"44":[35,198],"Gb/s":[36,155],"realized":[37,106],"single":[40],"IC":[41],"by":[42,80,94],"novel":[44],"feature":[45],"rate":[49,170,196],"selection":[50],"logic.":[51],"Input":[52],"are":[54,78,88],"sampled":[55],"with":[56],"eight":[57],"parallel":[58,96],"differential":[59],"master-slave":[60],"flip-flops,":[61],"where":[62],"bandwidth":[63],"enhancement":[64],"techniques":[65],"were":[66],"necessary":[67],"90":[69],"nm":[70],"CMOS.":[71],"Precise":[72],"low-jitter":[74],"local":[75,135],"phases":[77,87],"generated":[79],"an":[81],"analog":[82],"delay-locked":[83,110],"loop.":[84],"These":[85],"aligned":[89],"incoming":[92,131],"four":[95],"phase":[97],"rotators.":[98],"loop":[101,111],"CDR":[104,120,176,201],"is":[105,113,121],"as":[107],"digital":[109],"therefore":[114],"immune":[115],"against":[116],"process":[117],"tolerances.":[118],"able":[122],"track":[124],"maximum":[126],"frequency":[127],"deviation":[128],"of${\\pm":[129],"}{\\hbox{615~ppm}}$between":[130],"reference":[136],"fulfills":[139],"extended":[141],"XAUI":[142],"jitter":[143],"tolerance":[144],"mask.":[145],"A":[146],"bit":[147],"error":[148],"rate${\u226a}":[149],"\\hbox{10}^{-12}$was":[150],"verified":[151],"up":[152],"38":[154],"using":[156],"2$":[158],"^{7}":[159],"-$1":[160],"PRBS":[161],"pattern.":[162],"With":[163],"low":[165],"power":[166],"consumption":[167],"per":[168],"only":[172],"5.74":[173],"mW/(Gb/s)":[174],"meets":[177],"specifications":[179],"International":[182],"Technology":[183],"Roadmap":[184],"Semiconductors":[186],"90$~$nm":[188],"I/O-links":[191],"at":[192],"maximal":[194],"Gb/s.":[199],"occupies":[202],"chip":[204],"area":[205],"0.2${\\hbox{mm}}^{2}$.":[207]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":6},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}