{"id":"https://openalex.org/W2110921254","doi":"https://doi.org/10.1109/jssc.2009.2021447","title":"A 7 ps Jitter 0.053 mm&lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;$^{2}$&lt;/tex&gt;&lt;/formula&gt; Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC","display_name":"A 7 ps Jitter 0.053 mm&lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;$^{2}$&lt;/tex&gt;&lt;/formula&gt; Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2110921254","doi":"https://doi.org/10.1109/jssc.2009.2021447","mag":"2110921254"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2009.2021447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2021447","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109247172","display_name":"Dongsuk Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dongsuk Shin","raw_affiliation_strings":["Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","Hynix Semicond., Icheon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]},{"raw_affiliation_string":"Hynix Semicond., Icheon, South Korea","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102121626","display_name":"Janghoon Song","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Janghoon Song","raw_affiliation_strings":["Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea","[Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"[Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea]","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023963476","display_name":"Hyunsoo Chae","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyunsoo Chae","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea","[Department of Electronics and Electrical Engineering, Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"[Department of Electronics and Electrical Engineering, Samsung Electronics Company Limited, Hwasung, Kyunggi, South Korea]","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107422691","display_name":"Chulwoo Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chulwoo Kim","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.1035,"has_fulltext":false,"cited_by_count":66,"citation_normalized_percentile":{"value":0.96595378,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"44","issue":"9","first_page":"2437","last_page":"2451"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9181067943572998},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.6806244850158691},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5927814841270447},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5759760737419128},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.48430338501930237},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.44269272685050964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4279520511627197},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3973091244697571},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3403027653694153},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.32540684938430786},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2501356601715088},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20944350957870483},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18732091784477234}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9181067943572998},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.6806244850158691},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5927814841270447},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5759760737419128},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.48430338501930237},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.44269272685050964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4279520511627197},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3973091244697571},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3403027653694153},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.32540684938430786},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2501356601715088},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20944350957870483},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18732091784477234},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2009.2021447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2021447","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1533711155","https://openalex.org/W1540664825","https://openalex.org/W1558158353","https://openalex.org/W1974775547","https://openalex.org/W1997826936","https://openalex.org/W2031507986","https://openalex.org/W2034011126","https://openalex.org/W2057007249","https://openalex.org/W2063079402","https://openalex.org/W2098302131","https://openalex.org/W2101597431","https://openalex.org/W2117599119","https://openalex.org/W2124390946","https://openalex.org/W2130365397","https://openalex.org/W2160704142","https://openalex.org/W2162720403","https://openalex.org/W2169622190","https://openalex.org/W2538541815"],"related_works":["https://openalex.org/W2139484866","https://openalex.org/W2936029881","https://openalex.org/W2301158783","https://openalex.org/W2072077388","https://openalex.org/W2148370333","https://openalex.org/W2369998856","https://openalex.org/W2133120878","https://openalex.org/W1969806930","https://openalex.org/W3120154297","https://openalex.org/W2002107209"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11,36,48,59,69,79,85,93,98,111,119,146],"fast":[4,26],"lock":[5,27,134],"all-digital":[6,17],"delay-locked":[7],"loop":[8],"(ADDLL)":[9],"with":[10,35,68,105,129,145],"wide":[12,99,120],"range":[13,60,67,122],"and":[14,29,40,56,58,74,92,152],"high":[15,89],"resolution":[16,86],"duty":[18,32],"cycle":[19,33,94],"corrector":[20],"(ADDCC),":[21],"which":[22],"achieves":[23],"low":[24],"jitter,":[25,57],"time,":[28],"accurate":[30],"50%":[31],"correction":[34],"clock-synchronized":[37],"delay":[38],"(CSD)":[39],"time-to-digital":[41],"converter":[42],"(TDC)":[43],"schemes.":[44],"The":[45,76,102,136],"ADDLL":[46,104],"uses":[47],"self-calibration":[49],"scheme":[50],"to":[51,62,83,96,126],"reduce":[52],"the":[53,106,153],"phase":[54],"error":[55],"doubler":[61],"double":[63],"its":[64],"operating":[65,90],"frequency":[66,121],"negligible":[70],"increase":[71],"in":[72],"power":[73,147],"area.":[75],"ADDCC":[77,107],"employs":[78],"weighted":[80],"signal":[81],"generator":[82],"improve":[84],"problem":[87],"at":[88,142],"frequencies":[91],"detector":[95],"insure":[97],"operation":[100],"range.":[101],"proposed":[103],"was":[108],"fabricated":[109],"using":[110],"0.18":[112],"mum":[113],"CMOS":[114],"technology":[115],"that":[116],"operates":[117],"over":[118],"from":[123],"440":[124],"MHz":[125],"1.5":[127,143],"GHz":[128,144],"15":[130],"cycles":[131],"of":[132,149],"maximum":[133],"time.":[135],"peak-to-peak":[137],"jitter":[138],"is":[139,155],"7":[140],"ps":[141],"consumption":[148],"43":[150],"mW":[151],"area":[154],"0.053":[156],"mm":[157],"<sup":[158],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[159],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[160],".":[161]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":12},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":9},{"year":2012,"cited_by_count":10}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}