{"id":"https://openalex.org/W2098678283","doi":"https://doi.org/10.1109/jssc.2009.2014015","title":"Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits","display_name":"Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits","publication_year":2009,"publication_date":"2009-03-24","ids":{"openalex":"https://openalex.org/W2098678283","doi":"https://doi.org/10.1109/jssc.2009.2014015","mag":"2098678283"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2009.2014015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2014015","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036997390","display_name":"Muhammad Khellah","orcid":"https://orcid.org/0000-0001-9651-5639"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Muhammad Khellah","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, Hillsboro, OR#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037648751","display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["University of Wisconsin, Madison, Hillsboro, OR, USA","University of Wisconsin, Madison Madison, WI"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I135310074"]},{"raw_affiliation_string":"University of Wisconsin, Madison Madison, WI","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057969679","display_name":"Yibin Ye","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yibin Ye","raw_affiliation_strings":["Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Circuits Research Lab, Intel Corp, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corp, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006467285","display_name":"Dinesh Somasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Somasekhar","raw_affiliation_strings":["Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Circuits Research Lab, Intel Corp, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corp, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016416631","display_name":"Tanay Karnik","orcid":"https://orcid.org/0000-0003-0072-1492"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tanay Karnik","raw_affiliation_strings":["Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Circuits Research Lab, Intel Corp, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corp, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nitin Borkar","raw_affiliation_strings":["Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Circuits Research Lab, Intel Corp, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corp, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000042800","display_name":"Gunjan Pandya","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gunjan Pandya","raw_affiliation_strings":["Enterprise Microprocessor Group, Intel Corporation, Hillsboro, OR, USA","[Enterprise Microprocessor Group, Intel, Hillsboro, OR]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Enterprise Microprocessor Group, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"[Enterprise Microprocessor Group, Intel, Hillsboro, OR]","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","LTD Adv. Design, Intel Corp., Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"LTD Adv. Design, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009463405","display_name":"Tom Coan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Coan","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","LTD Adv. Design, Intel Corp., Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"LTD Adv. Design, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066037916","display_name":"Yih Wang","orcid":"https://orcid.org/0000-0002-4580-2870"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yih Wang","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","LTD Adv. Design, Intel Corp., Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"LTD Adv. Design, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Kevin Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhang","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","LTD Adv. Design, Intel Corp., Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"LTD Adv. Design, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049160185","display_name":"Clair Webb","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Clair Webb","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","LTD Adv. Design, Intel Corp., Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"LTD Adv. Design, Intel Corp., Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vivek De","raw_affiliation_strings":["Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","Circuits Research Lab, Intel Corp, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Circuits Research Laboratory, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Circuits Research Lab, Intel Corp, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":13,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.6621,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.930788,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"44","issue":"4","first_page":"1199","last_page":"1208"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.7455130815505981},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.7227160334587097},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4542839527130127},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43247509002685547},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4276469349861145},{"id":"https://openalex.org/keywords/stability","display_name":"Stability (learning theory)","score":0.4254935681819916},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4158289134502411},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.35963842272758484},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34244611859321594},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3404806852340698},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3258265256881714},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28752827644348145},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.23972547054290771},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.20349228382110596},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1922028660774231},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13208812475204468}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.7455130815505981},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.7227160334587097},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4542839527130127},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43247509002685547},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4276469349861145},{"id":"https://openalex.org/C112972136","wikidata":"https://www.wikidata.org/wiki/Q7595718","display_name":"Stability (learning theory)","level":2,"score":0.4254935681819916},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4158289134502411},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.35963842272758484},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34244611859321594},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3404806852340698},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3258265256881714},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28752827644348145},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.23972547054290771},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.20349228382110596},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1922028660774231},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13208812475204468},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2009.2014015","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2014015","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1549072435","https://openalex.org/W1565505009","https://openalex.org/W2001894083","https://openalex.org/W2033077089","https://openalex.org/W2049520384","https://openalex.org/W2096046678","https://openalex.org/W2098688943","https://openalex.org/W2099231065","https://openalex.org/W2100503779","https://openalex.org/W2101255991","https://openalex.org/W2125347149","https://openalex.org/W2126898248","https://openalex.org/W2128377660","https://openalex.org/W2132357267","https://openalex.org/W2149956781","https://openalex.org/W2171922263","https://openalex.org/W2543171663","https://openalex.org/W2738467824","https://openalex.org/W3148792909"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2104885411","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2339836056"],"abstract_inverted_index":{"This":[0,124],"paper":[1],"addresses":[2],"the":[3,139,160,177,212],"stability":[4,79],"problem":[5],"of":[6],"diffusion-notch-free":[7],"(DNF)":[8],"SRAM":[9,34,167],"cells":[10],"used":[11,30,158],"in":[12,31,40,147,169],"dense":[13],"last":[14],"level":[15],"caches":[16],"(LLC).":[17],"A":[18,150,206],"DNF":[19,58,109],"cell":[20,43,59,101,125],"eliminates":[21],"lithographic":[22],"induced":[23],"variations":[24],"due":[25],"to":[26,86,162,174],"nMOS":[27,140,221],"diffusion":[28],"notches":[29],"conventional":[32,148],"6T":[33],"cells.":[35],"However,":[36],"it":[37],"also":[38,122,214],"results":[39,184],"reduced":[41],"overall":[42],"stability.":[44,107,165],"We":[45],"describe":[46],"a":[47,55,87,144,198,202],"new":[48],"WL":[49],"under-drive":[50],"(WLUD)":[51],"circuit":[52,70,156],"that":[53,97,186],"enables":[54,197],"read":[56,128,132],"stable":[57,199],"with":[60,113,176,190],"all":[61],"minimally":[62],"sized":[63],"devices":[64],"(called":[65],"M-cell).":[66],"The":[67],"proposed":[68,178],"WLUD":[69,188],"is":[71,80,121,126,157],"both":[72],"PT":[73],"and":[74,117,130,182,224],"supply":[75],"noise":[76],"tolerant.":[77],"Write":[78],"maintained":[81],"at":[82],"low":[83,207],"voltage":[84,93,204,208],"thanks":[85],"V":[88,151,192,225],"<sub":[89,152,193,226],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[90,153,194,227],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">CC</sub>":[91,195],"dynamic":[92,100],"collapse":[94],"(DVC)":[95],"scheme":[96],"trades":[98],"large":[99],"retention":[102],"margin":[103,133],"for":[104,211],"improving":[105],"write":[106,164],"Another":[108],"cell,":[110],"called":[111],"P-cell,":[112],"pMOS":[114,219],"pass":[115],"device":[116],"charged":[118],"high":[119],"bit-lines":[120],"presented.":[123],"inherently":[127],"ratio-ed":[129],"extra":[131],"can":[134],"be":[135],"obtained":[136],"through":[137],"upsizing":[138],"PD":[141],"without":[142],"creating":[143],"notch":[145],"as":[146],"cell.":[149],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SS</sub>":[154,228],"DVC":[155,196],"along":[159,189],"P-cell":[161,213],"recover":[163],"Two":[166],"macros":[168],"45":[170],"nm":[171],"were":[172],"fabricated":[173],"experiment":[175],"schemes.":[179],"Both":[180],"simulation":[181],"measurement":[183],"confirm":[185],"~20%":[187],"proper":[191],"M-cell":[200],"across":[201],"wide":[203],"range.":[205],"operating":[209],"window":[210],"exists":[215],"by":[216],"appropriately":[217],"selecting":[218],"strength,":[220],"pull-down":[222],"size,":[223],"DVC.":[229]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}