{"id":"https://openalex.org/W2158933924","doi":"https://doi.org/10.1109/jssc.2009.2013766","title":"Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access","display_name":"Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access","publication_year":2009,"publication_date":"2009-02-26","ids":{"openalex":"https://openalex.org/W2158933924","doi":"https://doi.org/10.1109/jssc.2009.2013766","mag":"2158933924"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2009.2013766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2013766","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047952713","display_name":"Koji Nii","orcid":"https://orcid.org/0000-0002-9986-5308"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Koji Nii","raw_affiliation_strings":["Renesas Technology Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041951103","display_name":"Yasumasa Tsukamoto","orcid":"https://orcid.org/0000-0002-0963-6940"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasumasa Tsukamoto","raw_affiliation_strings":["Renesas Technology Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088276903","display_name":"Makoto Yabuuchi","orcid":"https://orcid.org/0000-0003-1515-4726"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Yabuuchi","raw_affiliation_strings":["Renesas Technology Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108532281","display_name":"Yasuhiro Masuda","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuhiro Masuda","raw_affiliation_strings":["Renesas Design Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Design Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045181951","display_name":"Susumu Imaoka","orcid":"https://orcid.org/0000-0003-4350-2337"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Susumu Imaoka","raw_affiliation_strings":["Renesas Design Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Design Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021640278","display_name":"Keiichi Usui","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Keiichi Usui","raw_affiliation_strings":["Daioh Electric Company Limited, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Daioh Electric Company Limited, Itami, Hyogo, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109904097","display_name":"S. Ohbayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shigeki Ohbayashi","raw_affiliation_strings":["Renesas Technology Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003278716","display_name":"Hiroshi Makino","orcid":"https://orcid.org/0000-0001-6444-133X"},"institutions":[{"id":"https://openalex.org/I72375662","display_name":"Osaka Institute of Technology","ror":"https://ror.org/02znffm54","country_code":"JP","type":"education","lineage":["https://openalex.org/I72375662"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroshi Makino","raw_affiliation_strings":["Osaka Institute of Technology, Hirakata, Osaka, Japan"],"affiliations":[{"raw_affiliation_string":"Osaka Institute of Technology, Hirakata, Osaka, Japan","institution_ids":["https://openalex.org/I72375662"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008563407","display_name":"Hirofumi Shinohara","orcid":"https://orcid.org/0000-0001-5589-8397"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hirofumi Shinohara","raw_affiliation_strings":["Renesas Technology Corporation, Itami, Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"Renesas Technology Corporation, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5047952713"],"corresponding_institution_ids":["https://openalex.org/I4210153176"],"apc_list":null,"apc_paid":null,"fwci":3.5889,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.93164025,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"44","issue":"3","first_page":"977","last_page":"986"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.677702784538269},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.612236738204956},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5415603518486023},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.5313715934753418},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48821476101875305},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.4453830122947693},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4081691801548004},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.35215455293655396},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.25838756561279297},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.233111172914505},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.15636011958122253},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14978647232055664},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10515713691711426}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.677702784538269},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.612236738204956},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5415603518486023},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5313715934753418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48821476101875305},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.4453830122947693},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4081691801548004},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.35215455293655396},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.25838756561279297},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.233111172914505},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.15636011958122253},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14978647232055664},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10515713691711426},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2009.2013766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2009.2013766","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W89786321","https://openalex.org/W1498071943","https://openalex.org/W1508193266","https://openalex.org/W1537523419","https://openalex.org/W1567119267","https://openalex.org/W1970601044","https://openalex.org/W1992606738","https://openalex.org/W1998359033","https://openalex.org/W1998649044","https://openalex.org/W2006292752","https://openalex.org/W2027019159","https://openalex.org/W2049520384","https://openalex.org/W2099231065","https://openalex.org/W2105402750","https://openalex.org/W2109104675","https://openalex.org/W2111833123","https://openalex.org/W2114578399","https://openalex.org/W2126275992","https://openalex.org/W2128743367","https://openalex.org/W2132357267","https://openalex.org/W2145563695","https://openalex.org/W2161934647","https://openalex.org/W2171922263","https://openalex.org/W2566219694","https://openalex.org/W3148792909","https://openalex.org/W4231296481","https://openalex.org/W6648341231"],"related_works":["https://openalex.org/W2217098757","https://openalex.org/W3208688275","https://openalex.org/W2088771128","https://openalex.org/W2730314563","https://openalex.org/W2120538654","https://openalex.org/W2058541779","https://openalex.org/W2971786152","https://openalex.org/W1632369502","https://openalex.org/W2288945810","https://openalex.org/W1980639873"],"abstract_inverted_index":{"We":[0,52],"propose":[1],"an":[2],"access":[3,30,33],"scheme":[4,31],"for":[5,61],"a":[6,54,72,97],"synchronous":[7],"dual-":[8],"port":[9],"(DP)":[10],"SRAM":[11],"that":[12],"minimizes":[13],"the":[14,43,63,79,109,114],"8T-DP-cell":[15,60],"area":[16],"and":[17,26],"maintains":[18],"cell":[19,64],"stability.":[20],"A":[21],"priority":[22],"row":[23],"decoder":[24],"circuit":[25],"shifted":[27],"bit-":[28],"line":[29],"eliminates":[32],"conflict":[34],"issues.":[35],"Using":[36],"65":[37],"nm":[38],"CMOS":[39],"technology":[40],"(hp90)":[41],"with":[42],"proposed":[44,115],"scheme,":[45],"we":[46],"fabricated":[47,80],"32":[48,81],"kB":[49,82],"DP-SRAM":[50],"macros.":[51],"obtained":[53],"0.71":[55],"mum":[56],"<sup":[57,88],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[58,89],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[59,90],"which":[62,92],"size":[65],"is":[66,85,93,104],"only":[67],"1.44":[68],"times":[69],"larger":[70,95],"than":[71,96],"6T-single-port":[73],"(SP)-":[74],"cell.":[75],"The":[76,101],"bit-density":[77],"of":[78,108,113],"DP-RAM":[83],"macro":[84],"667":[86],"kbit/mm":[87],",":[91],"25%":[94],"conventional":[98],"8T":[99],"SRAM.":[100],"standby":[102],"leakage":[103],"27%":[105],"less":[106],"because":[107],"small":[110],"drive-NMOS":[111],"transistor":[112],"8T-DP-cell.":[116]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}