{"id":"https://openalex.org/W2030921895","doi":"https://doi.org/10.1109/jssc.2008.2007144","title":"Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor","display_name":"Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W2030921895","doi":"https://doi.org/10.1109/jssc.2008.2007144","mag":"2030921895"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2008.2007144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2008.2007144","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057411329","display_name":"Georgios Konstadinidis","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"G.K. Konstadinidis","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052459623","display_name":"M. Tremblay","orcid":"https://orcid.org/0000-0003-2176-5902"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Tremblay","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057466049","display_name":"Shailender Chaudhry","orcid":"https://orcid.org/0009-0004-1852-1223"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Chaudhry","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075181146","display_name":"Mamun Rashid","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Rashid","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"P.F. Lai","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P.F. Lai","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048582869","display_name":"Yukio Otaguro","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Otaguro","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029422289","display_name":"Yannis Orginos","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Orginos","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000993753","display_name":"Sudhendra Parampalli","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Parampalli","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000055374","display_name":"Mark Steigerwald","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Steigerwald","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026130692","display_name":"Srinivasulu Gundala","orcid":"https://orcid.org/0000-0002-0415-1151"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Gundala","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006680922","display_name":"Rambabu Pyapali","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R. Pyapali","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033210993","display_name":"L. Rarick","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"L.D. Rarick","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073686732","display_name":"Ilyas Elkin","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I. Elkin","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111299225","display_name":"Yunxiu Ge","orcid":"https://orcid.org/0000-0003-2774-8978"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y. Ge","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053036341","display_name":"Ishwar Parulkar","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I. Parulkar","raw_affiliation_strings":["Sun MicroSystems, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc., Santa Clara, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":15,"corresponding_author_ids":["https://openalex.org/A5057411329"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.4839,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.92787506,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"44","issue":"1","first_page":"7","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.8809589147567749},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.745681643486023},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6655735969543457},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6263585686683655},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5944309830665588},{"id":"https://openalex.org/keywords/simultaneous-multithreading","display_name":"Simultaneous multithreading","score":0.5918254852294922},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4776122272014618},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.45830559730529785},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4468374252319336},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44623053073883057},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.44447365403175354},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.42705249786376953},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4204455316066742},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4196721017360687},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3983495235443115},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38279828429222107},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29212138056755066},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19269880652427673},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17795521020889282},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0793364942073822}],"concepts":[{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.8809589147567749},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.745681643486023},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6655735969543457},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6263585686683655},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5944309830665588},{"id":"https://openalex.org/C85717602","wikidata":"https://www.wikidata.org/wiki/Q82178","display_name":"Simultaneous multithreading","level":4,"score":0.5918254852294922},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4776122272014618},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.45830559730529785},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4468374252319336},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44623053073883057},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.44447365403175354},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.42705249786376953},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4204455316066742},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4196721017360687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3983495235443115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38279828429222107},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29212138056755066},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19269880652427673},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17795521020889282},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0793364942073822},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2008.2007144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2008.2007144","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5199999809265137,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320310968","display_name":"University of Patras","ror":"https://ror.org/017wvtq80"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1974295343","https://openalex.org/W2005646196","https://openalex.org/W2094754158","https://openalex.org/W2099089002","https://openalex.org/W2113751407","https://openalex.org/W2122892069","https://openalex.org/W2123608497","https://openalex.org/W2131647018","https://openalex.org/W2149778532","https://openalex.org/W2166766585","https://openalex.org/W4244583165","https://openalex.org/W4246178214"],"related_works":["https://openalex.org/W2118532220","https://openalex.org/W4240807263","https://openalex.org/W2913446311","https://openalex.org/W2150450196","https://openalex.org/W2294358097","https://openalex.org/W2482815832","https://openalex.org/W2133675875","https://openalex.org/W3142189107","https://openalex.org/W1594092496","https://openalex.org/W1558769186"],"abstract_inverted_index":{"This":[0,77],"third-generation":[1],"Chip-Multithreading":[2],"(CMT)":[3],"SPARC":[4],"processor":[5],"consists":[6],"of":[7,18,64,71,82],"16":[8],"cores":[9],"with":[10,112],"shared":[11],"memory":[12,98],"architecture":[13],"and":[14,32,38,58,86,92,102,109],"supports":[15],"a":[16,61,68],"total":[17],"32":[19,23],"main":[20],"threads":[21],"plus":[22],"scout":[24],"threads.":[25],"It":[26],"is":[27,33,48],"targeted":[28],"for":[29,35],"high-performance":[30],"servers,":[31],"optimized":[34],"both":[36],"single-":[37],"multi-threaded":[39],"applications.":[40],"The":[41],"396":[42],"mm":[43],"<sup":[44],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[45],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[46],"chip":[47],"fabricated":[49],"in":[50,97],"an":[51,80],"11":[52],"metal":[53],"layer":[54],"65-nm":[55],"CMOS":[56],"process":[57],"operates":[59],"at":[60,74],"nominal":[62],"frequency":[63],"2.3":[65],"GHz,":[66],"consuming":[67],"maximum":[69],"power":[70],"250":[72],"W":[73],"1.2":[75],"V.":[76],"paper":[78],"provides":[79],"overview":[81],"the":[83,88,107],"architectural":[84],"highlights":[85],"describes":[87],"physical":[89],"implementation":[90],"challenges":[91],"solutions":[93],"including":[94],"circuit":[95,110],"innovations":[96],"arrays,":[99],"register":[100],"files,":[101],"floating-point":[103],"hardware":[104],"that":[105],"boost":[106],"performance":[108],"robustness":[111],"low":[113],"area":[114],"overhead.":[115]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}