{"id":"https://openalex.org/W2159747318","doi":"https://doi.org/10.1109/jssc.2007.910957","title":"An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS","display_name":"An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2159747318","doi":"https://doi.org/10.1109/jssc.2007.910957","mag":"2159747318"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2007.910957","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2007.910957","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram Vangal","orcid":"https://orcid.org/0000-0003-1548-9876"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.R. Vangal","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102833447","display_name":"Jason Howard","orcid":"https://orcid.org/0009-0005-6250-6108"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Howard","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108382290","display_name":"Greg Ruhl","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Ruhl","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061796240","display_name":"Saurabh Dighe","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Dighe","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111050346","display_name":"H. Wilson","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Wilson","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067753561","display_name":"James Tschanz","orcid":"https://orcid.org/0000-0003-0317-4332"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Tschanz","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054988210","display_name":"D. Finan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Finan","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100634933","display_name":"A. Singh","orcid":"https://orcid.org/0000-0003-3186-3098"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Singh","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112441360","display_name":"Tiju Jacob","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Jacob","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090001638","display_name":"Shailendra Jain","orcid":"https://orcid.org/0000-0002-3391-1711"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Jain","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Erraguntla","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010693797","display_name":"Clark Roberts","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Roberts","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081186735","display_name":"Yatin Hoskote","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Hoskote","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Borkar","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Borkar","raw_affiliation_strings":["Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":77.2685,"has_fulltext":false,"cited_by_count":627,"citation_normalized_percentile":{"value":0.99954463,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"43","issue":"1","first_page":"29","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5957902669906616},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5781695246696472},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5755251049995422},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5399328470230103},{"id":"https://openalex.org/keywords/tile","display_name":"Tile","score":0.42630597949028015},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4104006290435791},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3689288794994354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35936129093170166},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2663778066635132},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.23674222826957703},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.22953349351882935},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1719578504562378},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.11746671795845032},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.109975665807724},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08316987752914429}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5957902669906616},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5781695246696472},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5755251049995422},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5399328470230103},{"id":"https://openalex.org/C2780728851","wikidata":"https://www.wikidata.org/wiki/Q468402","display_name":"Tile","level":2,"score":0.42630597949028015},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4104006290435791},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3689288794994354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35936129093170166},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2663778066635132},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.23674222826957703},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.22953349351882935},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1719578504562378},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.11746671795845032},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.109975665807724},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08316987752914429},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2007.910957","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2007.910957","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7699999809265137,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320310142","display_name":"Tulane University","ror":"https://ror.org/04vmvtb21"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1550639219","https://openalex.org/W1899064893","https://openalex.org/W1978358211","https://openalex.org/W2005345974","https://openalex.org/W2061171222","https://openalex.org/W2108911707","https://openalex.org/W2109681980","https://openalex.org/W2123184444","https://openalex.org/W2125357468","https://openalex.org/W2127639550","https://openalex.org/W2145071646","https://openalex.org/W2153733042","https://openalex.org/W2155385791","https://openalex.org/W2157373341","https://openalex.org/W2160642395","https://openalex.org/W2172212694","https://openalex.org/W4237249613","https://openalex.org/W6651790823","https://openalex.org/W6676231733","https://openalex.org/W6819126557"],"related_works":["https://openalex.org/W2114959296","https://openalex.org/W38346124","https://openalex.org/W2502442966","https://openalex.org/W2138666621","https://openalex.org/W2383936314","https://openalex.org/W1992771654","https://openalex.org/W2022661278","https://openalex.org/W2777914781","https://openalex.org/W4246369972","https://openalex.org/W4244869112"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3,12],"integrated":[4],"network-on-chip":[5],"architecture":[6],"containing":[7],"80":[8],"tiles":[9],"arranged":[10],"as":[11],"8x10":[13],"2-D":[14,50],"array":[15],"of":[16,57,102,107],"floating-point":[17,35],"cores":[18],"and":[19,72,116],"packet-switched":[20],"routers,":[21],"both":[22],"designed":[23],"to":[24],"operate":[25],"at":[26,113],"4":[27],"GHz.":[28],"Each":[29],"tile":[30],"has":[31],"two":[32],"pipelined":[33],"single-precision":[34],"multiply":[36],"accumulators":[37],"(FPMAC)":[38],"which":[39],"feature":[40],"a":[41,54,76,105],"single-cycle":[42],"accumulation":[43],"loop":[44],"for":[45],"high":[46],"throughput.":[47],"The":[48,60,93],"on-chip":[49],"mesh":[51],"network":[52],"provides":[53],"bisection":[55],"bandwidth":[56],"2":[58],"Terabits/s.":[59],"15-FO4":[61],"design":[62,88],"employs":[63],"mesochronous":[64],"clocking,":[65],"fine-grained":[66],"clock":[67],"gating,":[68],"dynamic":[69],"sleep":[70],"transistors,":[71],"body-bias":[73],"techniques.":[74],"In":[75],"65-nm":[77],"eight-metal":[78],"CMOS":[79],"process,":[80],"the":[81],"275":[82],"mm":[83],"<sup":[84],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[85],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[86],"custom":[87],"contains":[89],"100":[90],"M":[91],"transistors.":[92],"fully":[94],"functional":[95],"first":[96],"silicon":[97],"achieves":[98],"over":[99],"1.0":[100],"TFLOPS":[101],"performance":[103],"on":[104],"range":[106],"benchmarks":[108],"while":[109],"dissipating":[110],"97":[111],"W":[112],"4.27":[114],"GHz":[115],"1.07":[117],"V":[118],"supply.":[119]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":15},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":11},{"year":2020,"cited_by_count":15},{"year":2019,"cited_by_count":15},{"year":2018,"cited_by_count":18},{"year":2017,"cited_by_count":29},{"year":2016,"cited_by_count":43},{"year":2015,"cited_by_count":51},{"year":2014,"cited_by_count":51},{"year":2013,"cited_by_count":71},{"year":2012,"cited_by_count":88}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
