{"id":"https://openalex.org/W2077874318","doi":"https://doi.org/10.1109/jssc.2007.892185","title":"The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series","display_name":"The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series","publication_year":2007,"publication_date":"2007-04-01","ids":{"openalex":"https://openalex.org/W2077874318","doi":"https://doi.org/10.1109/jssc.2007.892185","mag":"2077874318"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2007.892185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2007.892185","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108484112","display_name":"Jonathan Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jonathan Chang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102100045","display_name":"Ming Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ming Huang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073889604","display_name":"Jonathan Shoemaker","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Shoemaker","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053128124","display_name":"John Benoit","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Benoit","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072672041","display_name":"Szu-Liang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Szu-Liang Chen","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100344362","display_name":"Wei Chen","orcid":"https://orcid.org/0000-0001-9550-0523"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Chen","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111494695","display_name":"Siufu Chiu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Siufu Chiu","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111827875","display_name":"Raghuraman Ganesan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Raghuraman Ganesan","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024422651","display_name":"G. Leong","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gloria Leong","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041739497","display_name":"Venkata Lukka","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Venkata Lukka","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037919423","display_name":"Stefan Rusu","orcid":"https://orcid.org/0000-0002-3322-9173"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stefan Rusu","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110151838","display_name":"Durgesh Srivastava","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Durgesh Srivastava","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Corporation, Santa Clara, CA#TAB#"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":12,"corresponding_author_ids":["https://openalex.org/A5108484112"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":6.4908,"has_fulltext":false,"cited_by_count":80,"citation_normalized_percentile":{"value":0.96550388,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"42","issue":"4","first_page":"846","last_page":"852"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.834955632686615},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.7226378917694092},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6909877061843872},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6544460654258728},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.5685126781463623},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5231446027755737},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.5048616528511047},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.474723219871521},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.47363749146461487},{"id":"https://openalex.org/keywords/pipeline-burst-cache","display_name":"Pipeline burst cache","score":0.46292993426322937},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.45994919538497925},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.44542187452316284},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.40092480182647705},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3771969676017761}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.834955632686615},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.7226378917694092},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6909877061843872},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6544460654258728},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5685126781463623},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5231446027755737},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.5048616528511047},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.474723219871521},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.47363749146461487},{"id":"https://openalex.org/C157547923","wikidata":"https://www.wikidata.org/wiki/Q7197276","display_name":"Pipeline burst cache","level":5,"score":0.46292993426322937},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.45994919538497925},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.44542187452316284},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.40092480182647705},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3771969676017761}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2007.892185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2007.892185","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/3","score":0.8700000047683716,"display_name":"Good health and well-being"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1567324233","https://openalex.org/W1899658488","https://openalex.org/W1978154694","https://openalex.org/W2077874318","https://openalex.org/W2164951898","https://openalex.org/W2788911864","https://openalex.org/W6633858208","https://openalex.org/W6684150898"],"related_works":["https://openalex.org/W2072955902","https://openalex.org/W2141363922","https://openalex.org/W2399041033","https://openalex.org/W2162744059","https://openalex.org/W2088347047","https://openalex.org/W3140186264","https://openalex.org/W12620440","https://openalex.org/W2000122388","https://openalex.org/W1576527819","https://openalex.org/W2397009038"],"abstract_inverted_index":{"The":[0],"16-way":[1],"set":[2],"associative,":[3],"single-ported":[4],"16-MB":[5],"cache":[6,36,56,66,72,75,88],"for":[7,70],"the":[8,34,49,55,65,87],"Dual-Core":[9],"Intel":[10],"Xeon":[11],"Processor":[12],"7100":[13],"Series":[14],"uses":[15],"a":[16,24,71,83],"0.624":[17],"mum":[18],"<sup":[19],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[20],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[21],"cell":[22],"in":[23,33,48],"65-nm":[25],"8-metal":[26],"technology.":[27],"Low":[28],"power":[29],"techniques":[30],"are":[31,46],"implemented":[32],"L3":[35],"to":[37],"minimize":[38],"both":[39],"leakage":[40,57],"and":[41,52,92],"dynamic":[42],"power.":[43],"Sleep":[44],"transistors":[45],"used":[47],"SRAM":[50],"array":[51],"peripherals,":[53],"reducing":[54],"by":[58],"more":[59],"than":[60],"2X.":[61],"Only":[62],"0.8%":[63],"of":[64],"is":[67],"powered":[68],"up":[69],"access.":[73],"Dynamic":[74],"line":[76],"disable":[77],"(Intel":[78],"Cache":[79],"Safe":[80],"Technology)":[81],"with":[82],"history":[84],"buffer":[85],"protects":[86],"from":[89],"latent":[90],"defects":[91],"infant":[93],"mortality":[94],"failures":[95]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":3}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}