{"id":"https://openalex.org/W2156896601","doi":"https://doi.org/10.1109/jssc.2006.888298","title":"An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme","display_name":"An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2156896601","doi":"https://doi.org/10.1109/jssc.2006.888298","mag":"2156896601"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2006.888298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2006.888298","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030096073","display_name":"Hiroki Fujisawa","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hiroki Fujisawa","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067261079","display_name":"S. Kubouchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shuichi Kubouchi","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056436703","display_name":"Koji Kuroki","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Koji Kuroki","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109371362","display_name":"Naohisa Nishioka","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Naohisa Nishioka","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015518079","display_name":"Yoshiro Riho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yoshiro Riho","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031739653","display_name":"Noda Hiromasa","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hiromasa Noda","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112265811","display_name":"Isamu Fujii","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Isamu Fujii","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068836168","display_name":"H. Yoko","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hideyuki Yoko","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022882912","display_name":"Ryuuji Takishita","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ryuuji Takishita","raw_affiliation_strings":["Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102271699","display_name":"Takahiro Ito","orcid":null},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takahiro Ito","raw_affiliation_strings":["Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058817454","display_name":"Hitoshi Tanaka","orcid":"https://orcid.org/0000-0003-1623-2650"},"institutions":[{"id":"https://openalex.org/I65143321","display_name":"Hitachi (Japan)","ror":"https://ror.org/02exqgm79","country_code":"JP","type":"company","lineage":["https://openalex.org/I65143321"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hitoshi Tanaka","raw_affiliation_strings":["Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Hitachi ULSI Systems Company Limited, Kokubunji, Tokyo, Japan","institution_ids":["https://openalex.org/I65143321"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079869175","display_name":"Masayuki NAKAMURA","orcid":"https://orcid.org/0000-0002-3671-7746"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Masayuki Nakamura","raw_affiliation_strings":["Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Development Office, Elpida Memory, Inc., Sagamihara, Kanagawa, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.2551,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.94244104,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"42","issue":"1","first_page":"201","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9915000200271606,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.6673060655593872},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.5538498163223267},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5213236212730408},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5133975744247437},{"id":"https://openalex.org/keywords/column","display_name":"Column (typography)","score":0.5105096101760864},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.48107075691223145},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.4778546988964081},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.45560896396636963},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.45556947588920593},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.44602668285369873},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4251837730407715},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.35821229219436646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.35527145862579346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33448541164398193},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3156144320964813},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2727094888687134},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27181726694107056},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2306627333164215},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.22637519240379333},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21052861213684082},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19351819157600403},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.09746098518371582},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.09616115689277649},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0846143364906311}],"concepts":[{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.6673060655593872},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.5538498163223267},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5213236212730408},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5133975744247437},{"id":"https://openalex.org/C2780551164","wikidata":"https://www.wikidata.org/wiki/Q2306599","display_name":"Column (typography)","level":3,"score":0.5105096101760864},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.48107075691223145},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.4778546988964081},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.45560896396636963},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.45556947588920593},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44602668285369873},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4251837730407715},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.35821229219436646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.35527145862579346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33448541164398193},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3156144320964813},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2727094888687134},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27181726694107056},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2306627333164215},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.22637519240379333},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21052861213684082},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19351819157600403},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.09746098518371582},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09616115689277649},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0846143364906311},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2006.888298","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2006.888298","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323314","display_name":"Fukuoka University","ror":"https://ror.org/04nt8b154"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1498916818","https://openalex.org/W2095923551","https://openalex.org/W2103610846","https://openalex.org/W2111965201","https://openalex.org/W2115809483","https://openalex.org/W2127729681","https://openalex.org/W2156896601","https://openalex.org/W2243540610","https://openalex.org/W2541375717","https://openalex.org/W6674626295"],"related_works":["https://openalex.org/W1530597339","https://openalex.org/W2336226224","https://openalex.org/W134340165","https://openalex.org/W2068131691","https://openalex.org/W1557286738","https://openalex.org/W2101018784","https://openalex.org/W2546695182","https://openalex.org/W3113336200","https://openalex.org/W4360765372","https://openalex.org/W2113029882"],"abstract_inverted_index":{"Three":[0],"circuit":[1],"techniques":[2],"for":[3],"an":[4,19],"8.1-ns":[5],"column-access":[6,36],"1.6-Gb/s/pin":[7,89],"512-Mb":[8],"DDR3":[9],"SDRAM":[10],"using":[11],"90-nm":[12],"dual-gate":[13],"CMOS":[14],"technology":[15],"were":[16],"developed.":[17],"First,":[18],"8:4":[20],"multiplexed":[21],"data-transfer":[22],"scheme,":[23],"which":[24],"operates":[25],"in":[26,35],"a":[27,32,45,63,92,97],"quasi-4-bit":[28],"prefetch":[29],"mode,":[30],"achieves":[31],"3.17-ns":[33],"reduction":[34],"time,":[37],"i.e.,":[38],"from":[39,57],"11.3":[40],"to":[41,59],"8.13":[42],"ns.":[43,61],"Second,":[44],"dual-clock":[46],"latency":[47,99],"counter":[48],"reduces":[49],"standby":[50],"power":[51,94],"by":[52],"22%":[53],"and":[54,78,96],"cycle":[55],"time":[56],"1.7":[58],"1.2":[60],"Third,":[62],"multiple-ODT-merged":[64],"output":[65],"buffer":[66],"enables":[67],"selection":[68],"of":[69,100],"five":[70],"effective-resistance":[71],"values":[72],"Rtt":[73],"(20,":[74],"30,":[75],"40,":[76],"60,":[77],"120":[79],"Omega)":[80],"without":[81],"increasing":[82],"I/O":[83],"capacitance.":[84],"Based":[85],"on":[86],"these":[87],"techniques,":[88],"operation":[90],"with":[91],"1.36-V":[93],"supply":[95],"column":[98],"7":[101],"was":[102],"accomplished":[103]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
