{"id":"https://openalex.org/W2021006328","doi":"https://doi.org/10.1109/jssc.2004.826319","title":"PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits","display_name":"PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits","publication_year":2004,"publication_date":"2004-05-01","ids":{"openalex":"https://openalex.org/W2021006328","doi":"https://doi.org/10.1109/jssc.2004.826319","mag":"2021006328"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2004.826319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2004.826319","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022381888","display_name":"Keiji Kishine","orcid":"https://orcid.org/0000-0003-3213-6650"},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"K. Kishine","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, Kanagawa, Japan","NTT Microsystem Integration Labs., Kanagawa, Japan"],"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"NTT Microsystem Integration Labs., Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113657018","display_name":"Kuniaki Fujimoto","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Fujimoto","raw_affiliation_strings":["NTT Electronics Corporation, Tokyo, Japan","[NTT Electronics Corporation, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"NTT Electronics Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"[NTT Electronics Corporation, Tokyo, Japan]","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059623367","display_name":"S. Kusanagi","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Kusanagi","raw_affiliation_strings":["NTT Electronics Corporation, Tokyo, Japan","[NTT Electronics Corporation, Tokyo, Japan]"],"affiliations":[{"raw_affiliation_string":"NTT Electronics Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"[NTT Electronics Corporation, Tokyo, Japan]","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002664379","display_name":"H. Ichino","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Ichino","raw_affiliation_strings":["NTT Microsystem Integration Laboratories, Kanagawa, Japan","[NTT Microsystem Integration Laboratories, Kanagawa, Japan]"],"affiliations":[{"raw_affiliation_string":"NTT Microsystem Integration Laboratories, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]},{"raw_affiliation_string":"[NTT Microsystem Integration Laboratories, Kanagawa, Japan]","institution_ids":["https://openalex.org/I2251713219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5022381888"],"corresponding_institution_ids":["https://openalex.org/I2251713219"],"apc_list":null,"apc_paid":null,"fwci":1.3166,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.8026234,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"39","issue":"5","first_page":"740","last_page":"750"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11429","display_name":"Semiconductor Lasers and Optical Devices","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.916216254234314},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.850396454334259},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.6992088556289673},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.5448505878448486},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5360861420631409},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.49402934312820435},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46852511167526245},{"id":"https://openalex.org/keywords/phase-margin","display_name":"Phase margin","score":0.44014236330986023},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4366534948348999},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2891956567764282},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22135955095291138},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14980226755142212},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13710856437683105},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.1280747354030609},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08662781119346619}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.916216254234314},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.850396454334259},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.6992088556289673},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.5448505878448486},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5360861420631409},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.49402934312820435},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46852511167526245},{"id":"https://openalex.org/C81455027","wikidata":"https://www.wikidata.org/wiki/Q7180955","display_name":"Phase margin","level":5,"score":0.44014236330986023},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4366534948348999},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2891956567764282},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22135955095291138},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14980226755142212},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13710856437683105},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.1280747354030609},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08662781119346619},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.0},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2004.826319","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2004.826319","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.5699999928474426,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1496424366","https://openalex.org/W1518553859","https://openalex.org/W1572713988","https://openalex.org/W1602813146","https://openalex.org/W1910378810","https://openalex.org/W1961334217","https://openalex.org/W2006082414","https://openalex.org/W2100264020","https://openalex.org/W2149020770","https://openalex.org/W2152719435","https://openalex.org/W2163143556","https://openalex.org/W2172236230","https://openalex.org/W2174322375"],"related_works":["https://openalex.org/W2181990889","https://openalex.org/W1975256196","https://openalex.org/W1990401855","https://openalex.org/W2194908547","https://openalex.org/W2962109748","https://openalex.org/W2054263477","https://openalex.org/W2023678153","https://openalex.org/W2172173484","https://openalex.org/W2018960023","https://openalex.org/W2049104631"],"abstract_inverted_index":{"A":[0],"design":[1,20],"technique":[2,137],"for":[3,45,62,155],"an":[4],"over-10-Gb/s":[5],"clock":[6,86,136,213],"and":[7,16,59,73,87,94,173],"data":[8,227],"recovery":[9],"(CDR)":[10],"IC":[11,123,165,208],"provides":[12],"good":[13,160],"jitter":[14,161,175,188],"tolerance":[15,176],"low":[17],"jitter.":[18],"To":[19],"the":[21,37,46,50,55,63,76,98,112,149,182,186,201,206,221],"CDR":[22,118,157,164,207],"using":[23,124,148],"a":[24,28,32,42,80,84,88,91,116,120,139,211,235],"PLL":[25,82,89,100],"that":[26,97,180],"includes":[27],"decision":[29],"circuit":[30],"with":[31,83,90,119,130,138,177],"certain":[33],"phase":[34,141,151],"margin":[35],"affecting":[36],"pull-in":[38,47,57,64,77],"performance,":[39],"we":[40,53,95,114],"derived":[41],"simple":[43],"expression":[44],"range":[48],"of":[49,79,104,111,225,239],"PLL,":[51],"which":[52,143,196],"call":[54],"\"limited":[56],"range,\"":[58],"used":[60,154],"it":[61],"performance":[65,78],"evaluation.":[66],"The":[67,134,163],"method":[68],"allows":[69],"us":[70],"to":[71,146,169,234],"quickly":[72],"easily":[74],"compare":[75],"conventional":[81],"full-rate":[85],"half-rate":[92,99,117,135,156],"clock,":[93],"verified":[96],"is":[101,144,190,197,228],"advantageous":[102],"because":[103],"its":[105],"wider":[106],"frequency":[107],"range.":[108],"For":[109],"verification":[110],"method,":[113],"fabricated":[115],"1:16":[121],"DEMUX":[122],"commercially":[125],"available":[126],"Si":[127],"bipolar":[128],"technology":[129],"f/sub":[131],"T/=43":[132],"GHz.":[133],"linear":[140],"detector,":[142],"adopted":[145],"avoid":[147],"binary":[150],"detector":[152],"often":[153],"ICs,":[158],"achieves":[159,174],"characteristics.":[162],"operates":[166],"reliably":[167],"up":[168],"over":[170],"15":[171],"Gb/s":[172],"wide":[178],"margins":[179],"surpasses":[181],"ITU-T":[183,202],"specifications.":[184],"Furthermore,":[185],"measured":[187],"generation":[189],"less":[191],"than":[192,200],"0.4":[193],"ps":[194],"rms,":[195],"much":[198],"lower":[199],"specification.":[203],"In":[204],"addition,":[205],"can":[209],"extract":[210],"precise":[212],"signal":[214],"under":[215],"harsh":[216],"conditions,":[217],"such":[218],"as":[219],"when":[220],"bit":[222],"error":[223],"rate":[224],"input":[226,238],"around":[229],"2/spl":[230],"times/10/sup":[231],"-2/":[232],"due":[233],"low-power":[236],"optical":[237],"-24":[240],"dBm.":[241]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}