{"id":"https://openalex.org/W2048572810","doi":"https://doi.org/10.1109/jssc.2002.808318","title":"Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era","display_name":"Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era","publication_year":2003,"publication_date":"2003-03-01","ids":{"openalex":"https://openalex.org/W2048572810","doi":"https://doi.org/10.1109/jssc.2002.808318","mag":"2048572810"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2002.808318","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.808318","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033141421","display_name":"C.H. Diaz","orcid":"https://orcid.org/0000-0002-7235-3636"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"C.H. Diaz","raw_affiliation_strings":["Device Engineering Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Device Engineering Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079257396","display_name":"Mi-Chang Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Mi-Chang Chang","raw_affiliation_strings":["Design Services Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Design Services Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073045141","display_name":"Tong-Chern Ong","orcid":null},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tong-Chern Ong","raw_affiliation_strings":["Device Engineering Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Device Engineering Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040725052","display_name":"J.Y.-C. Sun","orcid":"https://orcid.org/0000-0001-9216-2477"},"institutions":[{"id":"https://openalex.org/I4210120917","display_name":"Taiwan Semiconductor Manufacturing Company (Taiwan)","ror":"https://ror.org/02wx79d08","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210120917"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"J.Y.-C. Sun","raw_affiliation_strings":["Logic Technology Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Logic Technology Division, Research and Development, Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210120917"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5033141421"],"corresponding_institution_ids":["https://openalex.org/I4210120917"],"apc_list":null,"apc_paid":null,"fwci":2.782,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.90242914,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"38","issue":"3","first_page":"444","last_page":"449"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.6088747978210449},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5883944630622864},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5416470170021057},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5194408297538757},{"id":"https://openalex.org/keywords/interlock","display_name":"Interlock","score":0.5183278322219849},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4761379063129425},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44594964385032654},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44516605138778687},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.41280269622802734},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.330537885427475},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25772643089294434},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20756745338439941}],"concepts":[{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.6088747978210449},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5883944630622864},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5416470170021057},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5194408297538757},{"id":"https://openalex.org/C99535591","wikidata":"https://www.wikidata.org/wiki/Q1817095","display_name":"Interlock","level":2,"score":0.5183278322219849},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4761379063129425},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44594964385032654},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44516605138778687},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.41280269622802734},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.330537885427475},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25772643089294434},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20756745338439941},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2002.808318","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.808318","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1870293527","https://openalex.org/W2057675232","https://openalex.org/W2096912695","https://openalex.org/W2101975976","https://openalex.org/W2107766185","https://openalex.org/W2126810113","https://openalex.org/W2127177189","https://openalex.org/W2141553861","https://openalex.org/W2536554518","https://openalex.org/W2536698305","https://openalex.org/W2538063896","https://openalex.org/W2543003661","https://openalex.org/W2788477044"],"related_works":["https://openalex.org/W1497007238","https://openalex.org/W2046596376","https://openalex.org/W2789353574","https://openalex.org/W2380054458","https://openalex.org/W2061585006","https://openalex.org/W1487482626","https://openalex.org/W2390209095","https://openalex.org/W625299745","https://openalex.org/W2100563360","https://openalex.org/W1559639976"],"abstract_inverted_index":{"Several":[0],"physical":[1],"phenomena":[2],"in":[3,28,63,80],"highly":[4],"scaled":[5],"CMOS":[6],"technology":[7],"have":[8,37],"now":[9],"become":[10],"first-order":[11],"elements":[12],"affecting":[13],"the":[14,51,75,81],"electrical":[15],"behavior":[16],"of":[17,83],"transistor":[18],"characteristics.":[19,42],"Effects":[20],"such":[21],"as":[22],"STI":[23],"mechanical":[24],"stress,":[25],"direct":[26],"tunneling":[27],"gate":[29,31],"dielectrics,":[30],"line-edge":[32],"roughness,":[33],"and":[34,59],"others":[35],"can":[36],"significant":[38],"influence":[39],"on":[40,46],"device":[41,85],"This":[43],"paper":[44,72],"elaborates":[45],"these":[47],"effects":[48],"to":[49,65],"exemplify":[50],"need":[52,76],"for":[53,77],"closer":[54],"interaction":[55],"between":[56],"circuit":[57],"design":[58],"process":[60],"development":[61],"teams":[62],"order":[64],"push":[66],"out":[67],"application-dependent":[68],"scaling":[69],"limits.":[70],"The":[71],"also":[73],"highlights":[74],"further":[78],"efforts":[79],"areas":[82],"circuit-level":[84],"modeling.":[86]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}