{"id":"https://openalex.org/W2110654976","doi":"https://doi.org/10.1109/jssc.2002.1015684","title":"A fully integrated analog front-end macro for cable modem applications in 0.18-\u03bcm CMOS","display_name":"A fully integrated analog front-end macro for cable modem applications in 0.18-\u03bcm CMOS","publication_year":2002,"publication_date":"2002-07-01","ids":{"openalex":"https://openalex.org/W2110654976","doi":"https://doi.org/10.1109/jssc.2002.1015684","mag":"2110654976"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2002.1015684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.1015684","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031697378","display_name":"Andreas Wiesbauer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"A. Wiesbauer","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037630143","display_name":"Martin Clara","orcid":"https://orcid.org/0000-0001-6991-3391"},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"M. Clara","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067634694","display_name":"M. Harteneck","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"M. Harteneck","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071927284","display_name":"T. Potscher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"T. Potscher","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067593635","display_name":"B. Seger","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"B. Seger","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051269781","display_name":"Christoph Sandner","orcid":"https://orcid.org/0000-0002-3814-7476"},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"C. Sandner","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047122894","display_name":"C. Fleischhacker","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"C. Fleischhacker","raw_affiliation_strings":["Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","Dev. Center Villach, Infineon Technol. Austria, Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Development CenterVillach, Infineon Technologies Austria AG, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]},{"raw_affiliation_string":"Dev. Center Villach, Infineon Technol. Austria, Villach, Austria","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210131793"],"apc_list":null,"apc_paid":null,"fwci":1.03,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.76793235,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"37","issue":"7","first_page":"866","last_page":"873"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11160","display_name":"Acoustic Wave Resonator Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-front-end","display_name":"Analog front-end","score":0.745410144329071},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.731515645980835},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.5888900756835938},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.5724137425422668},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5154067277908325},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.47808384895324707},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.47518885135650635},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47278261184692383},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.4597170352935791},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.43555307388305664},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.43447840213775635},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.42433395981788635},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.4103381037712097},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3255589008331299},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17482054233551025}],"concepts":[{"id":"https://openalex.org/C2778870119","wikidata":"https://www.wikidata.org/wiki/Q16002927","display_name":"Analog front-end","level":3,"score":0.745410144329071},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.731515645980835},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.5888900756835938},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.5724137425422668},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5154067277908325},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.47808384895324707},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.47518885135650635},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47278261184692383},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.4597170352935791},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.43555307388305664},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.43447840213775635},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.42433395981788635},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.4103381037712097},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3255589008331299},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17482054233551025},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2002.1015684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.1015684","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1964521962","https://openalex.org/W2032105699","https://openalex.org/W2099679337","https://openalex.org/W2131785784","https://openalex.org/W2143854444","https://openalex.org/W2148550661"],"related_works":["https://openalex.org/W1532865199","https://openalex.org/W2019044074","https://openalex.org/W2742212520","https://openalex.org/W2744701634","https://openalex.org/W4247909714","https://openalex.org/W1988799405","https://openalex.org/W4391311879","https://openalex.org/W2079771749","https://openalex.org/W2146322466","https://openalex.org/W3144946090"],"abstract_inverted_index":{"An":[0],"analog":[1,23],"front-end":[2],"(AFE)":[3],"module":[4],"designed":[5],"for":[6,91],"use":[7],"together":[8],"with":[9,34],"a":[10,28,66,74,88],"digital":[11],"cable":[12,98],"modem":[13,99],"transceiver":[14],"on":[15],"one":[16],"single":[17],"die":[18],"is":[19,25],"presented.":[20],"All":[21],"the":[22,38,46,49,53,58],"functionality":[24],"implemented":[26],"in":[27],"pure":[29],"0.18-/spl":[30],"mu/m":[31],"CMOS":[32],"process":[33],"1.8-V":[35],"supply.":[36],"Besides":[37],"critical":[39],"requirements":[40],"toward":[41],"substrate":[42],"and":[43,57,73],"supply":[44],"isolation,":[45],"design":[47,90],"of":[48,69,77],"high-order":[50],"antialiasing":[51],"filter,":[52],"high-performance":[54],"analog-to-digital":[55],"converter,":[56],"low-jitter":[59],"phase-locked":[60],"loop":[61],"are":[62],"most":[63],"challenging.":[64],"With":[65],"silicon":[67],"area":[68],"9.9":[70],"mm/sup":[71],"2/":[72],"power":[75],"dissipation":[76],"less":[78],"than":[79],"1":[80],"W,":[81],"this":[82],"3-channel":[83],"AFE":[84],"can":[85],"be":[86],"considered":[87],"reference":[89],"first-IF":[92],"sampling":[93],"(surface":[94],"acoustic":[95],"wave":[96],"(SAW)-less)":[97],"systems.":[100]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
