{"id":"https://openalex.org/W2149247174","doi":"https://doi.org/10.1109/jssc.2002.1004578","title":"A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell","display_name":"A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell","publication_year":2002,"publication_date":"2002-06-01","ids":{"openalex":"https://openalex.org/W2149247174","doi":"https://doi.org/10.1109/jssc.2002.1004578","mag":"2149247174"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2002.1004578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.1004578","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110019918","display_name":"N. Shibata","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"N. Shibata","raw_affiliation_strings":["LSI Laboratories, Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan"],"affiliations":[{"raw_affiliation_string":"LSI Laboratories, Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101736927","display_name":"Masaki Watanabe","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Watanabe","raw_affiliation_strings":["Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026193740","display_name":"Y. Tanabe","orcid":null},"institutions":[{"id":"https://openalex.org/I2251713219","display_name":"NTT (Japan)","ror":"https://ror.org/00berct97","country_code":"JP","type":"company","lineage":["https://openalex.org/I2251713219"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Tanabe","raw_affiliation_strings":["Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Telegraph and Telephone Corporation, Atsugi, Kanagawa, Japan","institution_ids":["https://openalex.org/I2251713219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110019918"],"corresponding_institution_ids":["https://openalex.org/I2251713219"],"apc_list":null,"apc_paid":null,"fwci":0.6789,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.7159881,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"37","issue":"6","first_page":"735","last_page":"750"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6495872735977173},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.6412336826324463},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6242839097976685},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6034939885139465},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.596589207649231},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5690110921859741},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5084947347640991},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.4994814395904541},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.476915568113327},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.47340521216392517},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.45676469802856445},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4407289922237396},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.42164066433906555},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.4155384302139282},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40494009852409363},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3534920811653137},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3433408737182617},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.28988754749298096},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2537708878517151},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2396305501461029},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12586963176727295},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11731252074241638}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6495872735977173},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.6412336826324463},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6242839097976685},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6034939885139465},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.596589207649231},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5690110921859741},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5084947347640991},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4994814395904541},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.476915568113327},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.47340521216392517},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.45676469802856445},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4407289922237396},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.42164066433906555},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.4155384302139282},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40494009852409363},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3534920811653137},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3433408737182617},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.28988754749298096},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2537708878517151},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2396305501461029},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12586963176727295},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11731252074241638},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jssc.2002.1004578","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2002.1004578","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6899999976158142,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W178385260","https://openalex.org/W421161464","https://openalex.org/W1498566870","https://openalex.org/W1511662414","https://openalex.org/W1538689078","https://openalex.org/W1557333709","https://openalex.org/W1568019842","https://openalex.org/W1589482210","https://openalex.org/W1589495165","https://openalex.org/W1920677189","https://openalex.org/W1928851345","https://openalex.org/W1974068676","https://openalex.org/W1977537723","https://openalex.org/W1989248560","https://openalex.org/W1993518995","https://openalex.org/W2009634812","https://openalex.org/W2013373029","https://openalex.org/W2048810489","https://openalex.org/W2080856527","https://openalex.org/W2087679151","https://openalex.org/W2098023357","https://openalex.org/W2106691208","https://openalex.org/W2114516151","https://openalex.org/W2123653149","https://openalex.org/W2135841327","https://openalex.org/W2136604800","https://openalex.org/W2138549719","https://openalex.org/W2144828158","https://openalex.org/W2343594632","https://openalex.org/W2535025332","https://openalex.org/W2562739681","https://openalex.org/W6607356245","https://openalex.org/W6614681271","https://openalex.org/W6632111305","https://openalex.org/W6703991108"],"related_works":["https://openalex.org/W1528792662","https://openalex.org/W2116822261","https://openalex.org/W1928025959","https://openalex.org/W2158870714","https://openalex.org/W2121596400","https://openalex.org/W2136362177","https://openalex.org/W2027009856","https://openalex.org/W1978664845","https://openalex.org/W2039670496","https://openalex.org/W2108725798"],"abstract_inverted_index":{"First-in-first-out":[0],"(FIFO)":[1],"data":[2,39,89],"storages":[3],"are":[4,53],"in":[5,216,235],"great":[6],"demand":[7],"for":[8,21,196],"telecommunication":[9],"LSIs.":[10],"This":[11],"paper":[12],"presents":[13],"high-speed":[14],"and":[15,200,224],"low-power":[16,107],"CMOS":[17,183],"memory":[18,71,175],"techniques":[19],"specialized":[20],"FIFO":[22,61,174],"operation.":[23],"A":[24,147,169],"size-configurable":[25],"architecture":[26,113,151],"using":[27,98,127],"the":[28,35,57,82,87,106,119,128,133,137,144,157,198,204,236,242,246,254,258],"tile":[29],"methodology":[30],"is":[31,76,91,114,140,152,194,218,234],"employed":[32],"to":[33,55,93,105,116,155,250],"customize":[34],"word":[36],"counts":[37],"and/or":[38],"bits":[40,52],"with":[41,73,179,230,245,257],"a.":[42],"short":[43,186],"time":[44],"of":[45,60,81,123,136,160,190],"less":[46,219],"than":[47,220],"30":[48],"min.":[49],"Four":[50],"flag":[51],"introduced":[54],"inform":[56],"internal":[58],"state":[59],"memories.":[62],"To":[63],"obtain":[64],"a":[65,99,109,180,208],"higher":[66],"operating":[67,145],"speed,":[68],"an":[69],"SRAM-like":[70],"cell":[72],"current-sense":[74],"readout":[75],"used.":[77],"The":[78,213],"critical-path":[79],"delay":[80],"Gray-code":[83],"up/down":[84],"counter,":[85],"indicating":[86],"stored":[88],"volume,":[90],"shortened":[92],"6.0":[94],"ns":[95],"(66%)":[96],"by":[97],"double-rail":[100],"single-stage":[101],"XOR":[102],"circuit.":[103],"As":[104],"techniques,":[108],"wordline/bitline-swapped":[110],"dual-port":[111,228],"memory-cell":[112],"proposed":[115,154],"cut":[117],"off":[118],"static":[120],"power-supply":[121],"current":[122],"unselected":[124],"columns.":[125],"By":[126],"hidden":[129],"blanket-precharged":[130],"bitline":[131],"scheme,":[132],"power":[134,158,211,214],"dissipation":[135,159,215],"writing":[138],"circuitry":[139],"minimized":[141],"without":[142],"degrading":[143],"speed.":[146],"new":[148],"data-driven":[149],"gated-shift-pulse":[150],"also":[153],"reduce":[156],"shift-register-type":[161],"address":[162],"pointers":[163],"(1.5":[164],"mW":[165,240,252],"at":[166,207,226],"100":[167],"MHz).":[168],"2K-words":[170],"/spl":[171,192,222],"times/":[172],"8-bits":[173],"test":[176,248,260],"chip,":[177],"fabricated":[178],"0.6-/spl":[181],"mu/m":[182,193],"process":[184],"(a":[185],"effective":[187],"channel":[188],"length":[189],"0.35":[191],"available":[195],"both":[197],"nMOS":[199],"pMOS),":[201],"has":[202],"demonstrated":[203],"140-MHz":[205],"operation":[206,229],"typical":[209],"3.3-V":[210],"supply.":[212],"standby":[217],"0.1":[221],"mu/W":[223],"that":[225],"100-MHz":[227],"single":[231],"fan-out":[232],"loads":[233],"range":[237],"from":[238],"28":[239],"(in":[241,253],"best":[243],"case":[244,256],"M-scan":[247],"pattern)":[249],"46":[251],"worst":[255],"checkerboard":[259],"pattern).":[261]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}