{"id":"https://openalex.org/W1913006662","doi":"https://doi.org/10.1109/jproc.2015.2484299","title":"Technology-Dependent Logic Optimization","display_name":"Technology-Dependent Logic Optimization","publication_year":2015,"publication_date":"2015-10-23","ids":{"openalex":"https://openalex.org/W1913006662","doi":"https://doi.org/10.1109/jproc.2015.2484299","mag":"1913006662"},"language":"en","primary_location":{"id":"doi:10.1109/jproc.2015.2484299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jproc.2015.2484299","pdf_url":null,"source":{"id":"https://openalex.org/S68686220","display_name":"Proceedings of the IEEE","issn_l":"0018-9219","issn":["0018-9219","1558-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087632312","display_name":"Rajeev Murgai","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Rajeev Murgai","raw_affiliation_strings":["Synopsys India Private Ltd, Noida, India","[Synopsys India Private Ltd, Noida, India]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys India Private Ltd, Noida, India","institution_ids":[]},{"raw_affiliation_string":"[Synopsys India Private Ltd, Noida, India]","institution_ids":["https://openalex.org/I1335490905"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5087632312"],"corresponding_institution_ids":["https://openalex.org/I1335490905"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.02980348,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":"103","issue":"11","first_page":"2004","last_page":"2020"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9487882852554321},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6943296194076538},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.649703860282898},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.49537742137908936},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4891844093799591},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4798678457736969},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.47104549407958984},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4596104621887207},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.43711215257644653},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.4284970462322235},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.42259469628334045},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4186258912086487},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3719710409641266},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2893391251564026},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.23529022932052612},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2104445993900299},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.15341001749038696},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15042182803153992}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9487882852554321},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6943296194076538},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.649703860282898},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.49537742137908936},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4891844093799591},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4798678457736969},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.47104549407958984},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4596104621887207},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.43711215257644653},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.4284970462322235},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.42259469628334045},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4186258912086487},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3719710409641266},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2893391251564026},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.23529022932052612},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2104445993900299},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.15341001749038696},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15042182803153992},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jproc.2015.2484299","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jproc.2015.2484299","pdf_url":null,"source":{"id":"https://openalex.org/S68686220","display_name":"Proceedings of the IEEE","issn_l":"0018-9219","issn":["0018-9219","1558-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":67,"referenced_works":["https://openalex.org/W161275905","https://openalex.org/W1486898914","https://openalex.org/W1494117405","https://openalex.org/W1511688816","https://openalex.org/W1551597857","https://openalex.org/W1569550779","https://openalex.org/W1975465680","https://openalex.org/W1976809982","https://openalex.org/W1988808121","https://openalex.org/W1990053967","https://openalex.org/W1996535604","https://openalex.org/W2005559574","https://openalex.org/W2048312633","https://openalex.org/W2068674204","https://openalex.org/W2093513607","https://openalex.org/W2096250625","https://openalex.org/W2103626283","https://openalex.org/W2110445184","https://openalex.org/W2121494045","https://openalex.org/W2124752961","https://openalex.org/W2127340105","https://openalex.org/W2133743520","https://openalex.org/W2135250302","https://openalex.org/W2137406539","https://openalex.org/W2145126108","https://openalex.org/W2150430168","https://openalex.org/W2151784368","https://openalex.org/W2158927558","https://openalex.org/W2166011990","https://openalex.org/W2167099589","https://openalex.org/W2168126808","https://openalex.org/W2295333953","https://openalex.org/W2427843410","https://openalex.org/W3139969152","https://openalex.org/W3141004699","https://openalex.org/W3141295412","https://openalex.org/W4230111224","https://openalex.org/W4231151455","https://openalex.org/W4231437154","https://openalex.org/W4235645145","https://openalex.org/W4236913175","https://openalex.org/W4237162529","https://openalex.org/W4239259179","https://openalex.org/W4239906955","https://openalex.org/W4240274300","https://openalex.org/W4240866746","https://openalex.org/W4241713537","https://openalex.org/W4241987548","https://openalex.org/W4244029612","https://openalex.org/W4245901115","https://openalex.org/W4250956016","https://openalex.org/W4251585766","https://openalex.org/W4252129833","https://openalex.org/W4252615853","https://openalex.org/W4254483961","https://openalex.org/W4256548512","https://openalex.org/W4285719527","https://openalex.org/W6606550902","https://openalex.org/W6644650122","https://openalex.org/W6662583276","https://openalex.org/W6674422270","https://openalex.org/W6675345380","https://openalex.org/W6678075179","https://openalex.org/W6680613659","https://openalex.org/W6682537153","https://openalex.org/W6717835706","https://openalex.org/W6828239796"],"related_works":["https://openalex.org/W4245336546","https://openalex.org/W2123076670","https://openalex.org/W2038511870","https://openalex.org/W2126475478","https://openalex.org/W2075511834","https://openalex.org/W2543290882","https://openalex.org/W2326620043","https://openalex.org/W2068777369","https://openalex.org/W2157874690","https://openalex.org/W2146894108"],"abstract_inverted_index":{"In":[0,96],"modern":[1],"design":[2,49],"flows,":[3],"technology-dependent":[4,103],"logic":[5],"optimizations":[6],"consist":[7],"of":[8,42,109],"technology":[9,21],"mapping":[10,22],"and":[11,34,44,58,74,91,93],"transformations":[12],"applied":[13],"after":[14],"mapping.":[15],"Advances":[16],"have":[17],"been":[18],"made":[19],"in":[20,23,40],"the":[24,48,62,66,115],"last":[25],"decade.":[26],"However,":[27],"it":[28],"is":[29,78],"inherently":[30],"an":[31],"intractable":[32],"problem":[33],"state-of-the-art":[35],"algorithms":[36,101],"produce":[37],"suboptimal":[38],"netlists":[39],"terms":[41],"area":[43,75],"timing.":[45],"Also,":[46],"during":[47],"flow,":[50],"when":[51],"physical":[52],"information":[53],"becomes":[54],"available,":[55],"wire":[56],"loads":[57],"net":[59],"delays":[60],"change":[61],"timing":[63,73],"values":[64],"at":[65],"gates.":[67],"That":[68],"presents":[69],"opportunities":[70],"for":[71,102],"further":[72],"optimization.":[76],"This":[77],"accomplished":[79],"by":[80],"transforms":[81],"such":[82],"as":[83],"gate":[84,86],"sizing,":[85],"replication,":[87],"buffer":[88],"optimization,":[89],"restructuring":[90],"remapping,":[92],"pin":[94],"permutation.":[95],"this":[97],"paper,":[98],"we":[99],"survey":[100],"optimizations,":[104],"along":[105],"with":[106],"a":[107],"comparison":[108],"their":[110],"relative":[111],"power":[112],"to":[113],"optimize":[114],"netlist.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2022,"cited_by_count":2}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}