{"id":"https://openalex.org/W2171768221","doi":"https://doi.org/10.1109/jproc.2015.2392104","title":"Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology","display_name":"Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology","publication_year":2015,"publication_date":"2015-03-01","ids":{"openalex":"https://openalex.org/W2171768221","doi":"https://doi.org/10.1109/jproc.2015.2392104","mag":"2171768221"},"language":"en","primary_location":{"id":"doi:10.1109/jproc.2015.2392104","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jproc.2015.2392104","pdf_url":"https://ieeexplore.ieee.org/ielx7/5/7086369/07086413.pdf","source":{"id":"https://openalex.org/S68686220","display_name":"Proceedings of the IEEE","issn_l":"0018-9219","issn":["0018-9219","1558-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/5/7086369/07086413.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111492026","display_name":"Stephen Trimberger","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Stephen M. Trimberger","raw_affiliation_strings":["Xilinx, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Xilinx, San Jose, CA, USA","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5111492026"],"corresponding_institution_ids":["https://openalex.org/I32923980"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":31.618,"has_fulltext":true,"cited_by_count":209,"citation_normalized_percentile":{"value":0.99773071,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"103","issue":"3","first_page":"318","last_page":"331"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9444464445114136},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.6391764879226685},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5720005631446838},{"id":"https://openalex.org/keywords/factor","display_name":"Factor (programming language)","score":0.5543714761734009},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5484670996665955},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.46478769183158875},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.43458080291748047},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4171966016292572},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3257664442062378},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.27192747592926025},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20509541034698486},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.191804438829422},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15165701508522034},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11492222547531128}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9444464445114136},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.6391764879226685},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5720005631446838},{"id":"https://openalex.org/C2781039887","wikidata":"https://www.wikidata.org/wiki/Q1391724","display_name":"Factor (programming language)","level":2,"score":0.5543714761734009},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5484670996665955},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.46478769183158875},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.43458080291748047},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4171966016292572},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3257664442062378},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.27192747592926025},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20509541034698486},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.191804438829422},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15165701508522034},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11492222547531128},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jproc.2015.2392104","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jproc.2015.2392104","pdf_url":"https://ieeexplore.ieee.org/ielx7/5/7086369/07086413.pdf","source":{"id":"https://openalex.org/S68686220","display_name":"Proceedings of the IEEE","issn_l":"0018-9219","issn":["0018-9219","1558-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/jproc.2015.2392104","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jproc.2015.2392104","pdf_url":"https://ieeexplore.ieee.org/ielx7/5/7086369/07086413.pdf","source":{"id":"https://openalex.org/S68686220","display_name":"Proceedings of the IEEE","issn_l":"0018-9219","issn":["0018-9219","1558-2256"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.7400000095367432,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2171768221.pdf","grobid_xml":"https://content.openalex.org/works/W2171768221.grobid-xml"},"referenced_works_count":46,"referenced_works":["https://openalex.org/W1492991270","https://openalex.org/W1523051745","https://openalex.org/W1545914085","https://openalex.org/W1599892290","https://openalex.org/W1600749316","https://openalex.org/W1604136049","https://openalex.org/W1964175462","https://openalex.org/W1964761923","https://openalex.org/W1966573088","https://openalex.org/W1972395546","https://openalex.org/W1974169079","https://openalex.org/W1977850862","https://openalex.org/W1978615928","https://openalex.org/W2000921084","https://openalex.org/W2001824086","https://openalex.org/W2006312753","https://openalex.org/W2007049691","https://openalex.org/W2008694370","https://openalex.org/W2116094656","https://openalex.org/W2132275486","https://openalex.org/W2139637699","https://openalex.org/W2141597697","https://openalex.org/W2144141446","https://openalex.org/W2145767761","https://openalex.org/W2147139403","https://openalex.org/W2148658001","https://openalex.org/W2150405043","https://openalex.org/W2155814884","https://openalex.org/W2166029537","https://openalex.org/W2168244800","https://openalex.org/W2168732909","https://openalex.org/W2169333805","https://openalex.org/W2171769031","https://openalex.org/W2275304190","https://openalex.org/W3143893630","https://openalex.org/W4206412226","https://openalex.org/W6632842584","https://openalex.org/W6635877447","https://openalex.org/W6641528655","https://openalex.org/W6641859635","https://openalex.org/W6643345213","https://openalex.org/W6651700774","https://openalex.org/W6679517912","https://openalex.org/W6680692090","https://openalex.org/W6681672229","https://openalex.org/W6998728838"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W3033106587","https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2038220260","https://openalex.org/W1967938402","https://openalex.org/W3164085601","https://openalex.org/W2129019972","https://openalex.org/W1608572506","https://openalex.org/W2057745131"],"abstract_inverted_index":{"Since":[0],"their":[1,118],"introduction,":[2],"field":[3],"programmable":[4],"gate":[5],"arrays":[6],"(FPGAs)":[7],"have":[8,33,45,69,83],"grown":[9],"in":[10,21,73,95],"capacity":[11],"by":[12,23,36,48],"more":[13,37,58],"than":[14,38,60],"a":[15,24,39,80,128],"factor":[16,25,40],"of":[17,26,41,66,89,101,105,110,130,134],"10":[18],"$\\thinspace$000":[19],"and":[20,29,77,107,116,121],"performance":[22],"100.":[27],"Cost":[28],"energy":[30],"per":[31],"operation":[32],"both":[34],"decreased":[35],"1000.":[42],"These":[43,91],"advances":[44],"been":[46],"fueled":[47],"process":[49],"technology":[50,62],"scaling,":[51],"but":[52],"the":[53,131],"FPGA":[54,74],"story":[55],"is":[56],"much":[57],"complex":[59],"simple":[61],"scaling.":[63],"Quantitative":[64],"effects":[65],"Moore's":[67],"Law":[68],"driven":[70],"qualitative":[71],"changes":[72],"architecture,":[75],"applications":[76],"tools.":[78],"As":[79],"consequence,":[81],"FPGAs":[82],"passed":[84],"through":[85],"several":[86],"distinct":[87],"phases":[88],"development.":[90],"phases,":[92],"termed":[93],"\u201cAges\u201d":[94],"this":[96],"paper,":[97],"are":[98],"The":[99,103,108,124],"Age":[100,104,109,133],"Invention,":[102],"Expansion":[106],"Accumulation.":[111],"This":[112],"paper":[113,125],"summarizes":[114],"each":[115],"discusses":[117],"driving":[119],"pressures":[120],"fundamental":[122],"characteristics.":[123],"concludes":[126],"with":[127],"vision":[129],"upcoming":[132],"FPGAs.":[135]},"counts_by_year":[{"year":2026,"cited_by_count":5},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":18},{"year":2022,"cited_by_count":18},{"year":2021,"cited_by_count":20},{"year":2020,"cited_by_count":29},{"year":2019,"cited_by_count":30},{"year":2018,"cited_by_count":26},{"year":2017,"cited_by_count":19},{"year":2016,"cited_by_count":18},{"year":2015,"cited_by_count":4}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}