{"id":"https://openalex.org/W4415367133","doi":"https://doi.org/10.1109/jetcas.2025.3623865","title":"All-optical AND Logic Gate With High Extinction Ratio for Neural Network Hardware Implementation","display_name":"All-optical AND Logic Gate With High Extinction Ratio for Neural Network Hardware Implementation","publication_year":2025,"publication_date":"2025-10-20","ids":{"openalex":"https://openalex.org/W4415367133","doi":"https://doi.org/10.1109/jetcas.2025.3623865"},"language":"en","primary_location":{"id":"doi:10.1109/jetcas.2025.3623865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2025.3623865","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022242326","display_name":"Rita Asquini","orcid":"https://orcid.org/0000-0002-2898-9047"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Rita Asquini","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-2898-9047","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075556722","display_name":"Alessio Buzzin","orcid":"https://orcid.org/0000-0002-8071-5406"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessio Buzzin","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-8071-5406","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034684368","display_name":"Badrul Alam","orcid":"https://orcid.org/0000-0002-3052-7423"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Badrul Alam","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013731301","display_name":"Andrea Ceschini","orcid":"https://orcid.org/0000-0003-0555-9543"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Ceschini","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0003-0555-9543","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052397999","display_name":"Antonello Rosato","orcid":"https://orcid.org/0000-0002-4371-5925"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonello Rosato","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-4371-5925","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5015796693","display_name":"Massimo Panella","orcid":"https://orcid.org/0000-0002-9876-1494"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Panella","raw_affiliation_strings":["Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy"],"raw_orcid":"https://orcid.org/0000-0002-9876-1494","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza,”, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Department of Information Engineering, Electronics and Telecommunications, University of Rome “La Sapienza”, Via Eudossiana 18, Rome, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.24921665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":"1","first_page":"106","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10232","display_name":"Optical Network Technologies","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9703999757766724,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12611","display_name":"Neural Networks and Reservoir Computing","score":0.96670001745224,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6312000155448914},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6182000041007996},{"id":"https://openalex.org/keywords/ideal","display_name":"Ideal (ethics)","score":0.6011000275611877},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.38499999046325684},{"id":"https://openalex.org/keywords/optical-computing","display_name":"Optical computing","score":0.3837999999523163},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.38190001249313354},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.3449999988079071},{"id":"https://openalex.org/keywords/nor-logic","display_name":"NOR logic","score":0.34360000491142273},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.337799996137619}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6312000155448914},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6182000041007996},{"id":"https://openalex.org/C2776639384","wikidata":"https://www.wikidata.org/wiki/Q840396","display_name":"Ideal (ethics)","level":2,"score":0.6011000275611877},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5728999972343445},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5052000284194946},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.38499999046325684},{"id":"https://openalex.org/C148204187","wikidata":"https://www.wikidata.org/wiki/Q176541","display_name":"Optical computing","level":2,"score":0.3837999999523163},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.38190001249313354},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.3449999988079071},{"id":"https://openalex.org/C165862026","wikidata":"https://www.wikidata.org/wiki/Q670372","display_name":"NOR logic","level":5,"score":0.34360000491142273},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.337799996137619},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.33169999718666077},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.3248000144958496},{"id":"https://openalex.org/C21847791","wikidata":"https://www.wikidata.org/wiki/Q191081","display_name":"Logical conjunction","level":2,"score":0.3190000057220459},{"id":"https://openalex.org/C101991246","wikidata":"https://www.wikidata.org/wiki/Q5422078","display_name":"Extinction (optical mineralogy)","level":2,"score":0.31529998779296875},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.304500013589859},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2962999939918518},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.28380000591278076},{"id":"https://openalex.org/C101649071","wikidata":"https://www.wikidata.org/wiki/Q1359305","display_name":"Optical amplifier","level":3,"score":0.27720001339912415},{"id":"https://openalex.org/C101336846","wikidata":"https://www.wikidata.org/wiki/Q17105111","display_name":"Optical switch","level":2,"score":0.2750999927520752},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2703000009059906},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.2660999894142151},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.2508000135421753},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2500999867916107},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.2500999867916107}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/jetcas.2025.3623865","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2025.3623865","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/1753070","is_oa":false,"landing_page_url":"https://hdl.handle.net/11573/1753070","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4708119089","display_name":null,"funder_award_id":"NextGenerationEU - PE00000023 - CUPB53C22004170006","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G4746891580","display_name":null,"funder_award_id":"NextGenerationEU - CN00000013 - CUP B83C2200294000","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"},{"id":"https://openalex.org/G5671615935","display_name":null,"funder_award_id":"NextGenerationEU - PE00000001 - CUP B53C2200405000","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0,162],"development":[1],"of":[2,90,100,173],"optical":[3,20,102,112,184],"logic":[4,36],"gates":[5,175],"suitable":[6],"for":[7,32,52,87,170,182],"multi-stage":[8],"processes":[9],"is":[10],"a":[11,30,46,131],"central":[12],"issue":[13],"in":[14,80,105,153,165,179],"emerging":[15],"computational":[16],"applications":[17],"such":[18,55],"as":[19,56],"neural":[21,183],"networks.":[22],"In":[23],"this":[24],"work,":[25],"we":[26],"introduce":[27],"and":[28,59,74,114],"analyze":[29],"scheme":[31,66],"an":[33],"all-optical":[34],"AND":[35],"gate,":[37],"which":[38,96,155],"allows":[39],"to":[40,76,157,176],"have":[41],"almost":[42],"ideal":[43,79,88],"extinction":[44],"ratio,":[45],"feature":[47],"that":[48,125,142],"simplifies":[49],"cascaded":[50],"architectures":[51,181],"complex":[53],"operations":[54],"multibit":[57],"sums":[58],"multiplications.":[60],"We":[61,82],"analytically":[62],"demonstrate":[63],"how":[64],"our":[65,139,166],"forces":[67],"three":[68],"logical":[69,93,136],"states,":[70],"namely":[71],"\u201800\u2019,":[72],"\u201811\u2019":[73],"\u201810\u2019,":[75],"be":[77,177],"necessarily":[78],"behavior.":[81],"also":[83],"outline":[84],"the":[85,91,98,111,149,171],"conditions":[86,129],"behavior":[89],"remaining":[92],"state":[94],"\u201801\u2019,":[95],"requires":[97,156],"use":[99],"semiconductor":[101],"amplifiers":[103],"(SOA)":[104],"their":[106],"non-linear":[107],"operations,":[108],"by":[109,148],"tuning":[110],"input":[113],"feeding":[115],"current.":[116],"Our":[117],"numerical":[118],"analysis":[119],"on":[120],"symmetrically":[121],"balanced":[122],"SOAs":[123],"shows":[124],"there":[126],"are":[127,145,168],"multiple":[128],"enabling":[130],"very":[132],"small":[133,159],"output":[134],"at":[135],"\u201801\u2019;":[137],"also,":[138],"results":[140],"suggest":[141],"those":[143],"solutions":[144],"strongly":[146],"influenced":[147],"phase":[150],"shifts":[151],"induced":[152],"SOAs,":[154],"avoid":[158],"\u03b1":[160],"factors.":[161],"performance":[163],"outlined":[164],"transitions":[167],"promising":[169],"implementation":[172],"universal":[174],"deployed":[178],"future":[180],"computation.":[185]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-21T00:00:00"}