{"id":"https://openalex.org/W2811397962","doi":"https://doi.org/10.1109/jetcas.2018.2851749","title":"Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder","display_name":"Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder","publication_year":2018,"publication_date":"2018-06-29","ids":{"openalex":"https://openalex.org/W2811397962","doi":"https://doi.org/10.1109/jetcas.2018.2851749","mag":"2811397962"},"language":"en","primary_location":{"id":"doi:10.1109/jetcas.2018.2851749","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jetcas.2018.2851749","pdf_url":"https://ieeexplore.ieee.org/ielx7/5503868/8571018/08400590.pdf","source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://ieeexplore.ieee.org/ielx7/5503868/8571018/08400590.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073033950","display_name":"Vincent Camus","orcid":"https://orcid.org/0000-0003-4779-7742"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Vincent Camus","raw_affiliation_strings":["Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-4779-7742","affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060700384","display_name":"Mattia Cacciotti","orcid":"https://orcid.org/0000-0002-6038-7302"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Mattia Cacciotti","raw_affiliation_strings":["Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-6038-7302","affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090697759","display_name":"J\u00e9r\u00e9my Schlachter","orcid":"https://orcid.org/0000-0003-1483-3591"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Jeremy Schlachter","raw_affiliation_strings":["Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0003-1483-3591","affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069058393","display_name":"Christian Enz","orcid":"https://orcid.org/0000-0002-9968-5278"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Christian Enz","raw_affiliation_strings":["Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland"],"raw_orcid":"https://orcid.org/0000-0002-9968-5278","affiliations":[{"raw_affiliation_string":"Integrated Circuits Laboratory, \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":1.6413,"has_fulltext":true,"cited_by_count":25,"citation_normalized_percentile":{"value":0.84627091,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"8","issue":"4","first_page":"746","last_page":"757"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9677790403366089},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.707900881767273},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.638419508934021},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5682953000068665},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5461512804031372},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.48271414637565613},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.4747108519077301},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.46880558133125305},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4328475296497345},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4167467951774597},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3722323775291443},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.25528040528297424},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.208995521068573},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16855880618095398},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1493227779865265}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9677790403366089},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.707900881767273},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.638419508934021},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5682953000068665},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5461512804031372},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48271414637565613},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.4747108519077301},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.46880558133125305},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4328475296497345},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4167467951774597},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3722323775291443},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.25528040528297424},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.208995521068573},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16855880618095398},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1493227779865265},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/jetcas.2018.2851749","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jetcas.2018.2851749","pdf_url":"https://ieeexplore.ieee.org/ielx7/5503868/8571018/08400590.pdf","source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:infoscience.epfl.ch:255868","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/255868","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"research article"}],"best_oa_location":{"id":"doi:10.1109/jetcas.2018.2851749","is_oa":true,"landing_page_url":"https://doi.org/10.1109/jetcas.2018.2851749","pdf_url":"https://ieeexplore.ieee.org/ielx7/5503868/8571018/08400590.pdf","source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320320883","display_name":"Agence Nationale de la Recherche","ror":"https://ror.org/00rbzpz17"},{"id":"https://openalex.org/F4320320924","display_name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","ror":"https://ror.org/00yjd3n13"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2811397962.pdf","grobid_xml":"https://content.openalex.org/works/W2811397962.grobid-xml"},"referenced_works_count":37,"referenced_works":["https://openalex.org/W1532299620","https://openalex.org/W1534443887","https://openalex.org/W1538177026","https://openalex.org/W1730221140","https://openalex.org/W1996431812","https://openalex.org/W2045294186","https://openalex.org/W2053323369","https://openalex.org/W2072700980","https://openalex.org/W2077212538","https://openalex.org/W2083156986","https://openalex.org/W2100196964","https://openalex.org/W2101572961","https://openalex.org/W2121069160","https://openalex.org/W2124616298","https://openalex.org/W2129394555","https://openalex.org/W2132437582","https://openalex.org/W2135089667","https://openalex.org/W2155458498","https://openalex.org/W2160059864","https://openalex.org/W2267045640","https://openalex.org/W2394561232","https://openalex.org/W2402970300","https://openalex.org/W2510124007","https://openalex.org/W2537759401","https://openalex.org/W2589986623","https://openalex.org/W2612139336","https://openalex.org/W2613779579","https://openalex.org/W2742536119","https://openalex.org/W2743521949","https://openalex.org/W2775114336","https://openalex.org/W2890845652","https://openalex.org/W3147234326","https://openalex.org/W4229947305","https://openalex.org/W4250705145","https://openalex.org/W6634717524","https://openalex.org/W6669791407","https://openalex.org/W6738103153"],"related_works":["https://openalex.org/W2075110663","https://openalex.org/W1910495841","https://openalex.org/W2109236388","https://openalex.org/W2033419648","https://openalex.org/W2059369867","https://openalex.org/W4225135417","https://openalex.org/W2127980940","https://openalex.org/W2095962490","https://openalex.org/W2157955791","https://openalex.org/W2057091512"],"abstract_inverted_index":{"This":[0,25,39,67],"paper":[1],"introduces":[2],"a":[3,116],"novel":[4],"method":[5],"for":[6,146,160],"designing":[7],"approximate":[8,45,139,176],"circuits":[9],"by":[10],"fabricating":[11],"and":[12,35,80,98,140,148,157,162],"exploiting":[13],"false":[14],"timing":[15,30],"paths,":[16],"i.e.,":[17],"critical":[18],"paths":[19],"that":[20],"cannot":[21],"be":[22],"logically":[23],"activated.":[24],"allows":[26],"to":[27,43,125,172],"strongly":[28],"relax":[29],"constraints":[31],"while":[32,83,110],"guaranteeing":[33,84],"minimal":[34],"controlled":[36],"behavioral":[37],"change.":[38],"technique":[40],"is":[41,91,103,143],"applied":[42],"an":[44,134],"adder":[46],"architecture,":[47],"called":[48],"the":[49,60,71,75,166,169],"Carry":[50],"Cut-Back":[51],"Adder":[52],"(CCBA),":[53],"in":[54],"which":[55],"high-significance":[56],"stages":[57],"can":[58],"cut":[59],"carry":[61,76],"propagation":[62],"chain":[63],"at":[64],"lower-significance":[65],"positions.":[66],"lightweight":[68],"approach":[69],"prevents":[70],"logic":[72],"activation":[73],"of":[74,106,120,137,168],"chain,":[77],"improving":[78],"performance":[79],"energy":[81,122],"efficiency":[82],"low":[85],"worst-case":[86,149],"errors.":[87,151],"A":[88],"design":[89],"methodology":[90],"presented":[92],"along":[93],"with":[94,130],"implementation,":[95],"error":[96],"optimization,":[97],"design-space":[99],"minimization.":[100],"The":[101,152],"CCBA":[102,153],"proven":[104],"capable":[105],"extremely":[107],"high":[108],"accuracy":[109],"displaying":[111],"significant":[112],"circuit":[113],"savings.":[114],"For":[115],"worst":[117],"case":[118],"precision":[119],"99.999%,":[121],"savings":[123],"up":[124],"36%":[126],"are":[127],"demonstrated":[128],"compared":[129],"exact":[131],"adders.":[132],"Finally,":[133],"industry-oriented":[135],"comparison":[136],"32-bit":[138],"truncated":[141,158],"adders":[142,159],"carried":[144],"out":[145],"mean":[147],"relative":[150],"outperforms":[154],"both":[155],"state-of-the-art":[156],"high-accuracy":[161],"low-power":[163],"circuits,":[164],"confirming":[165],"interest":[167],"proposed":[170],"concept":[171],"help":[173],"building":[174],"highly-efficient":[175],"or":[177],"precision-scalable":[178],"hardware":[179],"accelerators.":[180]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":5},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}