{"id":"https://openalex.org/W2423451175","doi":"https://doi.org/10.1109/jetcas.2016.2571858","title":"Guest Editorial Emerging Memories\u2014Technology, Architecture and Applications (First Issue)","display_name":"Guest Editorial Emerging Memories\u2014Technology, Architecture and Applications (First Issue)","publication_year":2016,"publication_date":"2016-06-01","ids":{"openalex":"https://openalex.org/W2423451175","doi":"https://doi.org/10.1109/jetcas.2016.2571858","mag":"2423451175"},"language":"en","primary_location":{"id":"doi:10.1109/jetcas.2016.2571858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2016.2571858","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},"type":"editorial","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085567454","display_name":"Swaroop Ghosh","orcid":"https://orcid.org/0000-0001-8753-490X"},"institutions":[{"id":"https://openalex.org/I2613432","display_name":"University of South Florida","ror":"https://ror.org/032db5x82","country_code":"US","type":"education","lineage":["https://openalex.org/I2613432"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Swaroop Ghosh","raw_affiliation_strings":["Computer Science and Engineering, University of South Florida, Tampa, FL, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science and Engineering, University of South Florida, Tampa, FL, USA","institution_ids":["https://openalex.org/I2613432"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105554115","display_name":"Rajiv Joshi","orcid":"https://orcid.org/0009-0007-7486-1531"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajiv V. Joshi","raw_affiliation_strings":["IBM, Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"IBM, Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006467285","display_name":"Dinesh Somasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Somasekhar","raw_affiliation_strings":["Intel Inc., Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Intel Inc., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100353857","display_name":"Xin Li","orcid":"https://orcid.org/0000-0002-3811-2062"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xin Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5085567454"],"corresponding_institution_ids":["https://openalex.org/I2613432"],"apc_list":null,"apc_paid":null,"fwci":0.31904403,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.65704834,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"6","issue":"2","first_page":"105","last_page":"108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9866999983787537,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9840999841690063,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7509180307388306},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6618846654891968},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6535996794700623},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5583300590515137},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5179292559623718},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4940855801105499},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.49042007327079773},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.46320971846580505},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4527381956577301},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4236811101436615},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4171209931373596},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.37463295459747314},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3412942886352539},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2972041666507721},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.28560328483581543},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.28081220388412476},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2239614725112915},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.1399802565574646}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7509180307388306},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6618846654891968},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6535996794700623},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5583300590515137},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5179292559623718},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4940855801105499},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.49042007327079773},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.46320971846580505},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4527381956577301},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4236811101436615},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4171209931373596},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.37463295459747314},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3412942886352539},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2972041666507721},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.28560328483581543},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.28081220388412476},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2239614725112915},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.1399802565574646},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/jetcas.2016.2571858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2016.2571858","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6100000143051147,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4386903460","https://openalex.org/W2924367614","https://openalex.org/W2094308961","https://openalex.org/W2533585248","https://openalex.org/W2900372418","https://openalex.org/W2536264121","https://openalex.org/W4382618825","https://openalex.org/W4221167253","https://openalex.org/W2165816612","https://openalex.org/W2127643145"],"abstract_inverted_index":{"In":[0],"recent":[1],"nodes":[2],"the":[3,23,65,109,114,121,129,134,145,159,171],"technology":[4,157],"scaling":[5],"has":[6],"been":[7],"slow":[8],"and":[9,26,35,39,52,78,105,163,197],"affects":[10],"on":[11],"chip":[12],"memories":[13,99,137,177],"such":[14],"as":[15,150,152,178,183,185],"Static":[16],"Random":[17,44],"Access":[18,45],"Memories":[19],"(SRAMs).":[20],"They":[21,80],"have":[22,58],"smallest":[24],"dimension":[25],"besides":[27],"leakage":[28],"they":[29,69],"are":[30,70,75,87],"also":[31,76,81,125],"prone":[32],"to":[33,64,107,127,161,169,173],"process":[34],"environmental":[36],"variation.":[37],"Embedded":[38],"off-chip":[40],"memory":[41,56,154],"e.g.,":[42],"Dynamic":[43],"Memory":[46],"(DRAM)":[47],"suffers":[48],"from":[49,156],"standby":[50],"power":[51],"scalability":[53],"challenges.":[54],"Emerging":[55],"technologies":[57],"brought":[59],"a":[60],"lot":[61],"of":[62,92,132,136,175],"excitement":[63],"design":[66,122,155],"community":[67],"because":[68],"not":[71],"only":[72,138],"dense":[73],"but":[74],"scalable":[77],"energy-efficient.":[79],"possess":[82],"several":[83],"interesting":[84],"properties":[85],"that":[86],"desirable":[88],"for":[89,139,181],"wide":[90],"spectrum":[91],"applications.":[93,164],"Nevertheless,":[94],"designing":[95],"systems":[96,162],"using":[97],"emerging":[98,176],"requires":[100],"innovations":[101],"in":[102,120,148],"technology,":[103],"circuits/systems":[104],"applications":[106],"exploit":[108],"preferable":[110],"features":[111],"while":[112],"suppressing":[113],"limitations.":[115],"A":[116],"corresponding":[117],"paradigm":[118],"shift":[119],"methodology":[123],"is":[124,168],"required":[126],"break":[128],"conventional":[130],"mindset":[131],"limiting":[133],"usage":[135],"storage.":[140],"This":[141],"special":[142],"issue":[143],"covers":[144],"latest":[146],"trends":[147],"embedded":[149],"well":[151,184],"standalone":[153],"all":[158],"way":[160],"The":[165],"specific":[166],"message":[167],"motivate":[170],"readers":[172],"think":[174],"foundational":[179],"blocks":[180],"storage":[182],"non-storage":[186],"areas":[187],"including":[188],"search,":[189],"non-Boolean":[190],"computation,":[191],"data":[192],"analytics,":[193],"recognition,":[194],"neuromorphic":[195],"computing":[196],"so":[198],"on.":[199]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
