{"id":"https://openalex.org/W2108418905","doi":"https://doi.org/10.1109/jetcas.2012.2193837","title":"Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology","display_name":"Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W2108418905","doi":"https://doi.org/10.1109/jetcas.2012.2193837","mag":"2108418905"},"language":"en","primary_location":{"id":"doi:10.1109/jetcas.2012.2193837","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2012.2193837","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/178246","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054025554","display_name":"Giulia Beanato","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Giulia Beanato","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070054163","display_name":"Paolo Giovannini","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Paolo Giovannini","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013635152","display_name":"Alessandro Cevrero","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Alessandro Cevrero","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085969893","display_name":"Panagiotis Athanasopoulos","orcid":"https://orcid.org/0000-0002-0986-9031"},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Panagiotis Athanasopoulos","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080425779","display_name":"Michalis N. Zervas","orcid":"https://orcid.org/0000-0002-0651-4059"},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Michael Zervas","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082675293","display_name":"Yuksel Temiz","orcid":"https://orcid.org/0000-0001-9286-7864"},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Yuksel Temiz","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072423303","display_name":"Yusuf Leblebici","orcid":null},"institutions":[{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]},{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH","FR"],"is_corresponding":false,"raw_author_name":"Yusuf Leblebici","raw_affiliation_strings":["Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory, Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I29607241"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.1919,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.92422819,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"2","issue":"2","first_page":"295","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9843000173568726,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8498504757881165},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7241250276565552},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.566156268119812},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5095162987709045},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5056173801422119},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5054829120635986},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4880341589450836},{"id":"https://openalex.org/keywords/fan-out","display_name":"Fan-out","score":0.4870443642139435},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.44250404834747314},{"id":"https://openalex.org/keywords/stack","display_name":"Stack (abstract data type)","score":0.43819159269332886},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.42841649055480957},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4220576882362366},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.4144763946533203},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.385824054479599},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3527620732784271},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.3478914201259613},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.29723402857780457},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.25391900539398193},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.24614331126213074},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.1916142702102661},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10945934057235718},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09371572732925415}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8498504757881165},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7241250276565552},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.566156268119812},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5095162987709045},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5056173801422119},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5054829120635986},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4880341589450836},{"id":"https://openalex.org/C68812741","wikidata":"https://www.wikidata.org/wiki/Q636609","display_name":"Fan-out","level":3,"score":0.4870443642139435},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.44250404834747314},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.43819159269332886},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.42841649055480957},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4220576882362366},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.4144763946533203},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.385824054479599},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3527620732784271},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.3478914201259613},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.29723402857780457},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25391900539398193},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.24614331126213074},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.1916142702102661},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10945934057235718},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09371572732925415}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/jetcas.2012.2193837","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jetcas.2012.2193837","pdf_url":null,"source":{"id":"https://openalex.org/S142323794","display_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","issn_l":"2156-3357","issn":["2156-3357","2156-3365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.401.4815","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.401.4815","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:178246","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/178246","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:178246","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/178246","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":45,"referenced_works":["https://openalex.org/W57462620","https://openalex.org/W390323645","https://openalex.org/W1541633348","https://openalex.org/W1965451131","https://openalex.org/W1979566015","https://openalex.org/W2017503457","https://openalex.org/W2023264348","https://openalex.org/W2027712195","https://openalex.org/W2039277384","https://openalex.org/W2051909620","https://openalex.org/W2059807497","https://openalex.org/W2063740797","https://openalex.org/W2071003187","https://openalex.org/W2071208935","https://openalex.org/W2086481541","https://openalex.org/W2086716781","https://openalex.org/W2100597370","https://openalex.org/W2107304970","https://openalex.org/W2109321893","https://openalex.org/W2110886254","https://openalex.org/W2115246441","https://openalex.org/W2117816012","https://openalex.org/W2119911998","https://openalex.org/W2130517400","https://openalex.org/W2131413854","https://openalex.org/W2141248142","https://openalex.org/W2143807959","https://openalex.org/W2149809112","https://openalex.org/W2150871235","https://openalex.org/W2153215457","https://openalex.org/W2166803207","https://openalex.org/W2169589087","https://openalex.org/W2170501415","https://openalex.org/W2541408858","https://openalex.org/W2546189131","https://openalex.org/W3016205154","https://openalex.org/W3147911217","https://openalex.org/W3148993415","https://openalex.org/W4205976331","https://openalex.org/W6657224184","https://openalex.org/W6668307330","https://openalex.org/W6676662234","https://openalex.org/W6679697899","https://openalex.org/W6680950684","https://openalex.org/W6792983611"],"related_works":["https://openalex.org/W1544665014","https://openalex.org/W2748364266","https://openalex.org/W2069545207","https://openalex.org/W4243861219","https://openalex.org/W2556374054","https://openalex.org/W2092579166","https://openalex.org/W2969723039","https://openalex.org/W1977947048","https://openalex.org/W2906337187","https://openalex.org/W1591864685"],"abstract_inverted_index":{"An":[0],"innovative":[1],"modular":[2],"3-D":[3,37,86],"stacked":[4,16,121],"multi-processor":[5,80],"architecture":[6],"is":[7,11,135],"presented.":[8],"The":[9],"platform":[10],"composed":[12],"of":[13,102,137,143,151],"completely":[14],"identical":[15,49],"dies":[17,51],"connected":[18],"together":[19],"by":[20,35],"through-silicon-vias":[21],"(TSVs).":[22],"Each":[23],"die":[24,69],"features":[25],"four":[26],"32-bit":[27],"embedded":[28],"processors":[29],"and":[30,55,65,93,120],"associated":[31],"memory":[32],"modules,":[33],"interconnected":[34],"a":[36,75,85,112,140,147],"network-on-chip":[38],"(NoC),":[39],"which":[40],"can":[41,70],"route":[42],"packets":[43],"in":[44,84],"the":[45,60,89,95,100,132],"vertical":[46,148],"direction.":[47],"Superimposing":[48],"planar":[50],"minimizes":[52],"design":[53],"effort":[54],"manufacturing":[56],"costs,":[57],"ensuring":[58],"at":[59,139],"same":[61],"time":[62],"high":[63],"flexibility":[64],"reconfigurability.":[66],"A":[67],"single":[68],"be":[71],"used":[72],"either":[73],"as":[74],"fully":[76,105],"testable":[77],"standalone":[78],"chip":[79],"(CMP),":[81],"or":[82],"integrated":[83],"stack,":[87],"increasing":[88],"overall":[90],"core":[91],"count":[92],"consequently":[94],"system":[96],"performance.":[97],"To":[98],"demonstrate":[99],"feasibility":[101],"this":[103],"architecture,":[104],"functional":[106],"samples":[107],"have":[108],"been":[109],"fabricated":[110],"using":[111,122],"conventional":[113],"UMC":[114],"90":[115],"nm":[116],"complementary":[117],"metal-oxide-semiconductor":[118],"process":[119],"an":[123],"in-house,":[124],"via-last":[125],"Cu-TSV":[126],"process.":[127],"Initial":[128],"results":[129],"show":[130],"that":[131],"proposed":[133],"3-D-CMP":[134],"capable":[136],"operating":[138],"target":[141],"frequency":[142],"400":[144],"MHz,":[145],"supporting":[146],"data":[149],"bandwidth":[150],"3.2":[152],"Gb/s.":[153]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}