{"id":"https://openalex.org/W4240031511","doi":"https://doi.org/10.1109/iwsoc.2004.1319895","title":"A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology","display_name":"A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology","publication_year":2004,"publication_date":"2004-09-28","ids":{"openalex":"https://openalex.org/W4240031511","doi":"https://doi.org/10.1109/iwsoc.2004.1319895"},"language":"en","primary_location":{"id":"doi:10.1109/iwsoc.2004.1319895","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2004.1319895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023597395","display_name":"Azeddien M. Sllame","orcid":"https://orcid.org/0000-0002-0653-5896"},"institutions":[{"id":"https://openalex.org/I23906160","display_name":"University of Tripoli","ror":"https://ror.org/00taa2s29","country_code":"LY","type":"education","lineage":["https://openalex.org/I23906160"]}],"countries":["LY"],"is_corresponding":true,"raw_author_name":"A.M. Sllame","raw_affiliation_strings":["Faculty of Science, Computer Science Department, Al Fateh University, Libya"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Science, Computer Science Department, Al Fateh University, Libya","institution_ids":["https://openalex.org/I23906160"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5023597395"],"corresponding_institution_ids":["https://openalex.org/I23906160"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.27309148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"287","last_page":"290"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.9611999988555908,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.955299973487854,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.8010022640228271},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.7590159773826599},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7123686075210571},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.7052894830703735},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.6927568912506104},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6136705279350281},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5874608159065247},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5387118458747864},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5205722451210022},{"id":"https://openalex.org/keywords/test-bench","display_name":"Test bench","score":0.42246460914611816},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4214743971824646},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3614547848701477},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.31147634983062744},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20884358882904053}],"concepts":[{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.8010022640228271},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.7590159773826599},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7123686075210571},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.7052894830703735},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.6927568912506104},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6136705279350281},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5874608159065247},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5387118458747864},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5205722451210022},{"id":"https://openalex.org/C2776266606","wikidata":"https://www.wikidata.org/wiki/Q476482","display_name":"Test bench","level":2,"score":0.42246460914611816},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4214743971824646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3614547848701477},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.31147634983062744},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20884358882904053},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iwsoc.2004.1319895","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iwsoc.2004.1319895","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1592618590","https://openalex.org/W1595000105","https://openalex.org/W1885078729","https://openalex.org/W2023402165","https://openalex.org/W2024353582","https://openalex.org/W2064949444","https://openalex.org/W2124364081","https://openalex.org/W2149833539","https://openalex.org/W2155745491","https://openalex.org/W2157559950","https://openalex.org/W2490203607"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2075214143","https://openalex.org/W2376018793","https://openalex.org/W2070083638","https://openalex.org/W2911649771","https://openalex.org/W2148697719"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,44],"proposal":[4],"for":[5],"reusable":[6],"hardware":[7],"core":[8,39],"(component)":[9],"model.":[10],"The":[11,32],"model":[12,33],"is":[13],"designed":[14],"based":[15],"on":[16],"the":[17,21,23,49,54],"knowledge":[18],"gained":[19],"by":[20],"exploiting":[22],"design":[24],"space":[25],"exploration":[26],"methodology":[27],"presented":[28],"in":[29,41],"(Sllame,":[30],"2003).":[31],"structure":[34],"contains":[35],"component":[36,50],"characterization,":[37],"computation":[38],"specified":[40],"VHDL":[42],"language,":[43],"test":[45],"bench":[46],"to":[47],"smooth":[48],"integration":[51],"process":[52],"within":[53],"application":[55],"and":[56],"interfacing.":[57]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}